October 13 1995, Draft 1
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Chapter 7 Software Debugging
global registers are assigned to application use, and the remaining group of 32
(
gr64–gr95
) are for operating system use.
The processor does not assign any particular task to the global registers in the
operating system group. However, over time a convention has evolved among 29K
processor users. The subdivision of global registers
gr64–gr95
into sub groups was
described in section 3.3, and is widely adhered to; the methods presented in this chap-
ter shall continue with the convention.
The subgroups are known as: The interrupt Freeze mode temporaries (given
synonyms
it0–it3
); the operating system temporaries (
kt0–kt11
); and the operating
system static support registers (
ks0–ks15
).
7.2
PROCESSOR DEBUG SUPPORT
7.2.1 Execution Mode
The processor is in Supervisor mode whenever the SM–bit in the Current pro-
cessor Status register (CPS) is 1. If the SM bit is 0, the processor is executing in User
mode. When operating in User mode the processor cannot access protected re-
sources or execute privileged instructions.
Generally a processor maintains context information which refers to operating
system status and various user processes. Operating in User mode is a means of pre-
venting a User mode process from accessing information which belongs to another
task or information that the operating system wishes to keep hidden.
If a User mode task breaks any of the privilege rules described in the processor’s
User Manual, then a protection violation trap is taken. Traps cause the operating sys-
tem to regain control of execution. Typically the operating system will then send a
software signal to the User mode process reporting its violation and possibly stop-
ping its execution. The exact action which takes place is particular to each operating
system implementation.
Besides preventing User mode programs from using processor instructions
which are reserved for operating use only, an operating system can precisely control a
processes access to memory and registers. This can be very useful when debugging
User mode software. The following section describes the processor’s memory man-
agement support. The register protection scheme is very simple. Special register
RBP is used to restrict banks of global registers to Supervisor mode access only. Each
bank consists of 16 registers and a 1 in each RBP bit position restricts the correspond-
ing bank to Supervisor mode access only. Thus, it is normal to set RBP=0x3F, which
allows User mode processes to access global registers
gr96
and higher. These are the
only registers which can be affected by compiler generated code. Note however,
global registers
gr0
and
gr1
which perform special support tasks are effected by com-
piler generated code and their access is not restricted by the RBP protection scheme.