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Chapter 5 Operating System Issues
home–grown system could be constructed. The material covered in this chapter and
others should help in either constructing or selecting a suitable operating system. I
would certainly advice seriously considering purchasing rather than constructing.
The task may be enjoyable but probably more lengthy than most project time tables
will allow. However, for those who insist on building their own operating system,
AMD has a collection of useful routines which make a good starting point. Contact
AMD 29K customer support for a copy of the code.
There is usually no one right operating system. The choice depends on a number
of criteria which may vary from project to project. The following list presents several
questions which you need to ask yourself and possibly operating system vendors.
You can decide the importance of each item with regard your project requirements.
Are 3–bus family members as well as 2–bus members supported If the
Am29000 or Am29050 processors are to be used, and the data bus and
instruction bus are not to be tied together, then the operating system must be
clear about maintaining code and data in separate regions. The Harvard
architecture, supported by 3–bus memory systems, typically achieves a 20%
performance gain over 2–bus memory systems. Additionally, when 3–bus
systems are supported, the operating system may require the support of a
hardware bridge allowing the instruction memory to be reached (usually with
access delays) via a data memory access.
Are interruptible
SPILL
and
FILL
code supported By running them with
interrupts disabled the difficulties of performing repair of the register stack
support registers can be avoided, should they be interrupted. However, they
require the support of multi–cycle LOADM and STOREM instructions, which
results in increased interrupt latency. Additionally,
SPILL
and
FILL
support
with interrupts disabled, results in a larger overhead compared with
trampolining to support routines; thus it is non–optimal as
SPILL
ing and
FILL
ing occur a lot more often then their interruption.
Given that
SPILL
and
FILL
are interruptible, their operation is interdependent
with the
longjmp()
library routine and the signal trampoline code. All four of
these services must coordinate their manipulation of register stack support
registers if interrupts are to be reliably supported.
Some operating systems support nested interrupts, others do not; without nested
interrupt support, interrupt latency can be increased. The use of kernel threads
to complete interrupt processing is one way to keep down latency. If interrupt
handlers are to be written in a high level language such as C, it may be desirable
to support Freeze mode handlers in C. This greatly reduces the interrupt support
overhead, because the overhead of preparing the register stack for use by
non–leaf procedures is relatively high. Does the operating system under