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Chapter 8 Selecting a Processor
halfspeedbus
ramprecharge
rampprecharge 2
ramrefresh
false
1
;no Scalable Clocking
;DRAM precharge
255
;DRAM refresh
The LAPD program was linked and then simulated operating from DRAM– or
SRAM–only memory. Systems using mixed DRAM and SRAM were not modeled.
It is certainly possible to use SRAM; although the cost is likely to be relatively high,
given the generally large memory systems attached to 2–bus processors. However,
ROM devices are likely to be used with 2–bus processors; but since it is difficult to
achieve 1–cycle access with ROM, it is likely that data and code held in ROM would
be transferred to DRAM for faster access. Alternatively, an interleaved ROM system
may be constructed. This would enable 2/2 ROM to achieve 2/1 memory access;
resulting in much the same performance as 2/1 DRAM. In fact faster, as there is no
need to perform precharge when changing access to a new memory page.
The Am29050 3–bus processor results have been included with the 2–bus
results. The Am29050 is the only member of the 3–bus processor group which is
likely to be selected for a new design. A 2–bus processor such as the Am29030 offers
as much performance as a 3–bus Am29000; and also offers a simpler system design,
as well as an easier upgrade path. The inclusion of a floating–point execution unit
within the Am29050 makes it an attractive choice for floating–point intensive
operations. Two–bus processors perform floating–point operations using emulation
routines generally accessed via traps. This is slower than the direct execution
achieved with the Am29050. However, the Am29040 can perform integer multiply
directly in hardware (other 2–bus processors use emulation), this assists the task of
emulating missing floating–point operations. Consequently, the Am29040 processor
is an alternative to the Am29050 when an application requires fast floating–point
support. The LAPD benchmark does not contain any floating–point operations.
Hence, it is not a suitable benchmark for evaluating processors for floating–point
operation.
16 MHz Memory Systems
This is the entry level system speed for 2–bus processors. The Am29035 is the
only processor offered at this speed. However, using Scalable Clocking an Am29030
or Am29040 operating at 33 MHz internally, can be combined with a 16 MHz
memory system. When Scalable Clocking is used, off–chip instruction and data
access is performed at the slower 16 MHz memory system speed. The higher cost of
the faster processors makes these systems more expensive, but a considerably more
powerful systems is achieved. Figure 8-6 shows performance results for various
systems based on 16 MHz memory systems.
The performance of the systems improve in accordance with the availability of
faster memory. Given that all 2–bus 29K processors contain instruction cache,
off–chip access is mainly required for instruction cache reload. Caches which