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Chapter 5 Operating System Issues
Data loads performed to memory locations which are marked non cachable are
not subject to data intervention. There is never any internal delaying of data in case
data intervention occurs
late
in the access. Hence, the critical word can be accessed in
a minimum of 2–cycles –– given a 2–cycle memory system. This requires that a data
region which is not cached by a processors, also not be cached by any other processor
(in a multiprocessor system).
With virtual addressing in use, the MMU can be configured to select a
write–through policy on a per–page bases. The write–through policy ensures that
data in external memory is always consistent with data held in cache as all load
instructions are applied to memory (and to the cache if they hit). Selecting this policy
for all memory pages would result in a poorer overall performance compared to the
default copy–back policy. However, regions of address space may be allocated to
peripherals which require immediate update. For example, video memory should be
marked as write–through rather than cachable. There is a definite advantage to
accessing video frame information from the cache when manipulating images.
Additionally, system implementations which fail to deal with the additional
hardware signals needed to support bus snooping may use write–through access to
assist with cache coherence problems. A write–through policy would only enable an
external
agent
to read shared data, it would not be able to modify the data.
To achieve the best performance, application code will likely use the data cache
with copy–back operation selected. However, there are situations when an
application will prefer write–through cache operation –– at least for portions of the
memory space. Memory locations are frequently used to pass data between operating
system and application code. If the operating system where to use copy–back data
cache operation (the default), there would be a danger that some data blocks
(accessed by the operating system) would be cached and their M bit set; later when
returning to the application, the block may be within a memory page which is marked
write–through, this would prevent the block being copied–back should the block be
reallocated. It is best to run the operating system with address translation turned on.
This enables the MMU to control the cache operation for memory pages which are
jointly accessed by the operating system and application code. To simplify this task,
the configuration register has an Freeze–PD (FPD) bit. When this bit is set the
Physical Data (PD) bit in the CPS registers is not set when the operating system is
entered via a trap or interrupt. The FPD bit enables the PD bit to remain unchanged.
Thus, if address translation was enabled in the application, it will remain enabled
after a trap or interrupt. The data cache need not be disabled when the operating
system is entered. However, the MMU must ensure a consistent cache policy for
memory pages which are jointly accessed by operating system and application code.
The Am29040 processor deals with other agents, such as a DMA controller,
accessing the same memory by performing bus snooping. Multiprocessor designs,
with on–chip caches, are also supported by the snooping protocol. The Shared (S) bit