
2
Evaluating and Programming the 29K RISC Family
large number of registers to reduce the need to fetch data from off–chip memory.
When external memory is accessed it is via explicit load and store operations, and
never via extended instruction addressing modes. The large number of registers,
within the processor’s register file, act effectively as a cache for program data. How-
ever, the implementation of a multiport register file is superior to a conventional data
cache as it enables simultaneous access to multiple operands.
Parameter passing between procedure calls is supported by dynamically sized
register windows. Each procedure’s register window is allocated from a stack of 128
32–bit registers. This results in a very efficient procedure call mechanism, and is re-
sponsible for considerable operational benefits compared to the typical CISC meth-
od of pushing and popping procedure parameters from a memory stack.
Processors in the 29K family also make use of other techniques usually
associated with RISC, such as delayed branching, to keep the instruction hungry
RISC fed and prevent pipeline stalling.
The freedom from microcode not only benefits the effectiveness of the instruc-
tion processing stream, but also benefits the interrupt and trap mechanism required to
support such events as external hardware interrupts. The preparations performed by
29K hardware for interrupt processing are very brief, and this
lightweight approach
enables programmers to define their own interrupt architecture; enabling optimiza-
tions to be selected which are best for, say, interrupt through put, or short latency in
commencing handler processing.
The 29K family includes 3–bus Harvard memory architecture processors,
2–bus processors which have simplified and flexible memory system interfaces, and
microcontrollers with considerable on–chip system support. The range is extensive,
yet User mode instruction compatibility is achieved across the entire family [AMD
1993a]. Within each family–grouping, there is also pin compatibility. The family
supports the construction of a scalable product range with regard to performance and
system cost. For example, all of the performance of the top–end processor configura-
tions may not be required, or be appropriate, in a product today but it may be neces-
sary in the future. Because of the range and scalability of the family, making a com-
mitment to 29K processor technology is an investment supported by the ability to
scale–down or scale–up a design in the future. Much of the family’s advantages are
attained by the flexibility in memory architecture choice. This is significant because
of the important impact a memory system can have on performance, overall cost, and
design and test time [Olson 1988][Olson 1989].
The microcontroller family members contain all the necessary RAM and ROM
interface glue–logic on–chip, permitting memory devices to be directly connected to
the processor. Given that memory systems need only be 8–bit or 16–bit wide, the
introduction of these devices should hasten the selection of embedded RISC in future
product designs. The use of RISC need not be considered an expensive option in
terms of system cost or hardware and software design times. Selecting RISC is not