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Chapter 8 Selecting a Processor
have slow ROM, or ROMs which are only 8–bits wide. Having slow or narrow ROM
can help to keep the system cost down. The program must be copied from ROM to
DRAM after processor power up. Hence, the DRAM is the only memory which
influences program execution speeds. Unlike Am2924x microcontrollers the
Am2920x processors have no Translation Look–Aside Buffers (TLBs).
Consequently, they can not protect the DRAM from accidental damage during
program execution This may be more of an issue during code development than in a
final production product.
It is important to note here that the Am29205 processor does not have a
BOOTW (boot width) pin, and hence must initially operate from 16–bit wide
memory. Only the Am29200 processor operation can be initiated from 8–bit ROM.
Consequently, DRAM–only systems are more applicable to the Am29200. This is a
little unfortunate as only the Am29205 is available at the lower cost 12.5 MHz
frequency. Highlighted on Figure 8-5 are the simulation results for an Am29200
processor operating at 16 MHz using DRAM–only (16 R=*/* D=3/2).
The second type of system of interest uses 16–bit ROM (2/2) with 16–bit
DRAM (3/2). This is faster than operating from DRAM–only. If ROM is to be used it
must at least support 2/2 access or faster. Additionally, it must be 16–bits wide. If it is
slower or narrower it is best to execute from DRAM–only. A 12.5 MHz Am29205
with ROM (2/2) and DRAM (3/2) has 97% of the performance of a 16 MHz
Am29200 operating at 16 MHz with DRAM–only.
The third type of system of interest uses 1/1 SRAM. Given the higher cost of
SRAM compared to DRAM, this configuration is only applicable when extra
performance is required. The SRAM–only systems shown in Figure 8-5 would
require an 8–bit ROM for program initialization –– much the same as DRAM–only
systems. The simulation results show that a 16–bit DRAM–only system has only
79% of the performance of an 8–bit 1/1 SRAM system. The 8–bit SRAM system has
2% more performance than the 16–bit 2/2–3/2 system (ROM–DRAM). The reason
for the higher performance can be understood by examining the number of cycles
required to fetch a single 32–bit instruction. With a 16–bit 3/2 DRAM–only system,
6–cycles are required to fetch the first instruction; 4–cycles for burst–mode fetched
instructions. With 8–bit 1/1 SRAM, 4–cycles are required to fetch instructions. The
8–bit SRAM has the advantage.
Building a 16–bit SRAM system which is 1/1 produces a system which has
140% of the performance of a 16–bit DRAM–only system. At 12.5 MHz,
single–cycle access requires 13 ns SRAM, which is readily available. Simple SRAM
based designs can offer surprisingly good performance but the small size of SRAM
devices results in the systems only being suitable for applications requiring small
amounts of memory. Otherwise the cost of the SRAM is likely to be prohibitively
high.