
17
Chapter 1 Architectural Overview
operation is very similar to the Am29030 processor. It is only available at lower clock
frequencies, compared with its close relative. And with half the amount of instruction
cache memory, it contains one set of the two sets provided by the Am29030. That is, it
has 4k bytes of instruction memory cache which is directly mapped. Consequently it
can be expected to operate with reduced overall performance.
In all other aspects it is the same as the Am29030 processor, except it has Pro-
grammable Bus Sizing which the Am29030 processor does not. Programmable Bus
Sizing provides for lower cost system designs. The processor can be dynamically
programmed (via the configuration register) to operate with a 16–bit instruction/data
bus, performing both read and write operations. When the option is selected, 32–bit
data is accessed by the processor hardware automatically performing two consecu-
tive accesses. The ability to operate with 16–bit and 32–bit memory systems makes
the 2–bus 29K family members well suited to scalable system designs, in terms of
cost and performance.
1.6
THE Am29040 2–BUS MICROPROCESSOR
The Am29040
processor is pin compatible with other 2–bus members of the
family (see Table 1-2). The processor was introduced in 1994 and offers higher per-
formance than the 2–bus Am29030; it also has a number of additional system support
facilities.
There is an enhanced instruction cache, now 8k bytes; which is tagged in much
the same way as the Am29030’s instruction cache, except there are four valid bits per
cache block (compared to the Am29030’s one bit per block). Partially filled blocks
are supported, and block reload begins with the first required instruction (target of a
branch) rather than the first instruction in the block. An additional benefit of having a
valid bit per–instruction rather than per–block is that load or store instructions can
interrupt cache reload. With the Am29030 processor, once cache reload had started,
it could not be postponed or interrupted by a higher priority LOAD instruction.
The Am29040 was the first 29K microprocessor to have a data cache. The 4k
byte data cache is physically addressed and supports both “copy–back” and “write–
through” policies. Like other 29K Family members, the data cache always operates
with physical addresses and cache blocks are only allocated on LOAD instructions
which miss (a “read–allocate” or “l(fā)oad–allocate” policy). The block size is 16 bytes
and there is one valid bit per block. This means that complete data blocks must be
fetched when data cache reload occurs. Burst mode addressing is used to reload a
block, starting with the first word in the block. The addition of a data cache makes the
Am29040 particularly well–suited to high–performance data handling applications.
The default data cache policy is “copy–back”. A four word copy–back buffer is
used to improve the performance of the copy–back operation. Additionally, cache
blocks have an M bit–field, which becomes set when data in the block is modified. If