
207
Chapter 4 Interrupts and Traps
mtsr
iret
pc0,it0
;restore PC0
The example code begins by saving the Program Counters (PC0 and PC1), us-
ing MFSR instructions to move the values from special registers to temporary global
registers
it0
and
it1
.
Freeze mode is then disabled by clearing the FZ bit in the CPS register. (Note the
bits set by the MTSRIM instruction are system implementation dependent; the RE bit
may be required.) Once Freeze mode is turned off, the ALU register will be modified
by any ALU/Logical operation. Thus, it is important that the ALU register be saved
now. (Note that two processor cycles are needed, after Freeze mode is removed, to
allow the program state to properly update the program counters.)
If interrupts are not to be re-enabled and the kernel does not require the use of
global registers (
kt0–kt2
), then these registers can be used to extend the number of
available interrupt temporary registers.
The ALU register is saved in temporary kernel register
it3.
The Channel regis-
ters (CHA, CHD and CHC) are then saved in operating system temporary registers
kt0–kt2.
The interrupt handler is still executing with interrupts disabled at this point in
the program, but load- and store-multiple instructions can be freely used, as long as
they do not cause another interrupt or trap to occur. Note, even with the DA bit in the
CPS register set, certain traps such as a Data Access Exception can still be taken.
When the handler is finished, it must reverse the process by restoring all the saved
registers. No particular order of instructions is necessary, as long as Freeze mode is
entered before PC1 and PC0 are restored. Additionally, instructions affecting the
ALU register must not be used after the saved value has been restored. By restoring
the ALU unit after Freeze mode is entered, instructions are prevented from affecting
the ALU register.
When the IRET instruction is executed, the restored Program Counters
(PC0–PC1) are used to resume the interrupted program. The restored CPS (saved in
OPS by the CPU) and Channel register contents are used to restart any unfinished
operations.
If enough global registers are not available for saving the Program Counters and
Channel registers, memory could be used for this purpose. In this case, six words of
memory are needed. Example code for saving and restoring the registers in the user’s
memory stack is shown below. Note, the
pushsr
and
popsr
macro instructions first
introduced in section 3.3.1 (page 119), are used in the example code and are presented
again below:
.macro
mfsr
sub
store
.endm
pushsr,sp,reg,sreg
reg,sreg
sp,sp,4
0,0,reg,sp