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Chapter 4 Interrupts and Traps
Instructions that use special registers––these instructions may be used;
however, any modified registers may have to be saved and restored before the
interrupt handler returns. The EXTRACT and INSERT instructions are in this
category.
Instructions that modify special registers–– because of the normal side effect of
their operation, these instructions must be used with caution. There are three
subgroups within this group:
—Arithmetic and logical instructions that set the Z, N, V, and C status bits in the
ALU Status register. These instructions can be used in Freeze mode if the ALU
status bits are not used. Because Freeze mode disables updating the ALU Status
register, extended precision arithmetic instructions, such as ADDC or
SUBC,
will not execute properly.
—Load-Multiple and Store Multiple. These instructions cannot be used in Freeze
mode, because the Channel registers (CHA, CHD, and CHC) upon which their
execution depends are frozen.
—LOAD and STORE instructions with the set BP option enabled, if the Data
Width Enable (DW bit) is 0. In this case, if BP must be set, it will have to
be done explicitly by using a Move-To-Special Register (MTSR) instruction.
Therefore, LOAD and STORE instructions with word-aligned addresses (i.e.,
those whose least significant 2 bits are 0) may be used without additional effort;
however, if byte or half-word instructions are needed, the BP register must be
explicitly set prior to execution of a non-word-aligned LOAD, STORE,
INSERT, or EXTRACT instruction.
All other instructions may be used without restriction, keeping in mind the in-
herent implications of Freeze mode. (Note: Other restrictions apply to Am29000
processors manufactured prior to revision C.)
4.3.5 Monitor mode
Monitor mode only applies to the Am29050 processor. If a trap occurs when the
DA bit in the CPS register is a 1, the processor starts executing at address 16 in
instruction ROM space. Monitor mode is not entered as a result of asynchronous
events such as timer interrupts or activation of the TRAP(1–0) or INTR(3–0) lines.
On taking a Monitor mode trap the Reason Vector register (RSN) is set to indi-
cate the cause of the trap. Additionally, the MM bit in the CPS register is set to 1.
When the MM bit is set, the shadow program counters (SPC0, SPC1, and SPC2) are
frozen, in a similar way to the FZ bit freezing the PC0–PC2 registers. Because the
shadow program counters continue to record PC-bus activity when the FZ bit is set,
they can be used to restart Freeze mode execution. This is achieved by an IRET or
IRETINV instruction being executed while in Monitor mode.