
44
Evaluating and Programming the 29K RISC Family
The Am29240 processor supports integer multiply directly in a single cycle.
Most 29K processors take a trap when an integer multiply is attempted. It is left to
trapware to emulate the
missing
instruction. The ability to perform high speed multi-
ply makes the processor a better choice for calculation intensive applications such as
digital signal processing. Note, floating–point performance should also improve
with the Am29240 as floating–point emulation routines can make use of the integer
multiply instruction.
The Am2924x family grouping is implemented with a silicon process which en-
ables processors to operate at 3.3–volts or 5–volts. The lower power consumption
achievable at 3.3–volts makes the Am29240 suitable for hand–held type applica-
tions.
1.9.1 The Am29243 Microcontroller
The Am29243 is an Am29240 microcontroller enhanced to deal with commu-
nication applications (see Table 1-4). For this reason the video interface is omitted.
The pins used have not been reassigned, and there is a possibility they will be allo-
cated in a future microcontroller for an additional communications support function.
Communication applications frequently require large amounts of DRAM, and it
is often critical that no corruption of the data occur. Parity error checking is often per-
formed by memory systems with the objective of detecting data corruption. It can be
difficult to built the necessary circuitry at high memory system speeds. The
Am29243 microcontroller has built–in parity generation and checking for all DRAM
accesses. When enabled by the DRAM controller, the processor will take trap num-
ber 4 when a parity error is detected. Having parity handling built–in enables single–
cycle DRAM accesses to be performed without any external circuitry required.
Because of the larger amounts of memory typically used in communication ap-
plications, the Am29243 has a second Translation Look–Aside Buffer (TLB). Hav-
ing two TLBs enables a larger number of virtual to physical address translations to be
cached (held in a TLB register) at any time. This reduces the TLB reload overhead.
The second TLB also has 16 entries (8 sets, two entries per set), and the page size can
be the same or different. If the TLB page sizes are the same, a four–way set associa-
tive MMU can be constructed with supporting software. Alternatively one TLB can
be used for code and the second, with a larger page size, for data buffers or shared
libraries. The TLB entries have a Global Page (GLB) bit; when set the mapped page
can be accessed by any processes regardless of its process identifier (PID).
1.9.2 The Am29245 Microcontroller
The Am29245 is a low–cost version of the Am29240 microcontroller (see
Table 1-4). To enable the lower cost, the data cache and the integer multiply unit have
been omitted. Further, there are only two DMA channels in place of the Am29240’s
four. To further reduce cost, one of the two serial ports has also been omitted.