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Chapter 1 Architectural Overview
tute two of the four external access spaces. The other two are the ROM space and the
coprocessor space. The ROM space is accessed via the instruction bus. Like the
instruction space it covers a 2
32
range.
1.10.1 General Purpose Registers
All members of the family have general purpose registers which are made up
from 128
local
registers and more than 64
global
registers (see Figure 1-14). These
registers are the primary source and destination for most 29K instructions. Instruc-
tions have three 8–bit operand fields which are used to supply the addresses of gener-
al registers. All User mode executable instructions and code produced by high level
language compilers, are restricted to only directly assessing general purpose regis-
ters. The fact that these registers are all 32–bit and that there is a large number of
them, vis–a–vis CISC, reduces the need to access data held in external memory.
General purpose registers are implemented by a multiport register file. This file
has a minimum of three access ports, the Am29050 processor has an additional port
for writing–back floating–point results. Two of the three ports provide simultaneous
read access to the register file; the third port is for updating a register value. Instruc-
tions generally specify two general purpose register operands which are to be oper-
ated on. After these operands have been presented to the execution unit, the result of
the operation is made available in the following cycle. This allows the result of an
integer operation to be written back to the selected general purpose register in the
cycle following its execution. At any instant, the current cycle is used to write–back
the result of the previous computation.
The Am29050 can execute floating–point operations in parallel with integer
operations. The latency of floating–point instructions can be more than the 1–cycle
achieved by the integer operation unit. Floating–point results are written back, when
the operation is complete, via their own write–back port, without disrupting the inte-
ger units ability to write results into the general purpose register file.
Global Registers
The 8–bit operand addressing fields enable only the lower 128 of the possible
256 address values to be used for
direct
general purpose register addressing. This is
because the most significant address bit is used to select a register base–plus–offset
addressing mode. When the most significant bit is zero, the accessed registers are
known as Global Registers. Only the upper 64 of the global registers are implement-
ed in the register file. These registers are known as
gr64–gr127
. Some of the lower
address–value global registers are assigned special support tasks and are not really
general purpose registers.
The Am29050 processor supports a condition code accumulator with global
registers
gr2
and
gr3
. The accumulator can be used to concatenate the result of sever-
al Boolean comparison operations into a single condition code. Later the accumu-