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Chapter 4 Interrupts and Traps
turns control to the Process Dispatcher, which selects the next queue entry and turns
control over to high-level Handler-2.
During this execution, one more Interrupt-1 event occurs, which results in the
creation of another queue entry. This entry is processed when high-level Handler-2
finishes its execution and the
Process Dispatcher again receives control.
High-level Handler-1 processes the remaining data and returns control to the
Process Dispatcher which, upon finding no more queue entries, returns to the inter-
rupted user process.
Each execution of the interrupt processes Interrupt-1 or Interrupt-2, as well as
the Process Dispatcher and high-level Handler-1
and
high-level Handler-2
code seg-
ments, is quite short; however, with the short execution approach, individual inter-
rupt priorities are not taken into account. If priority handling of interrupts is impor-
tant, a different approach is needed. For example, entries could be linked into a single
queue, with their position in the queue determined by their priority. In this case, more
sophisticated queue handling procedures would have to be implemented; however, a
given high-level handler would still execute to completion before another handler is
given control.
To handle fully-nested priority-oriented interrupts, that is the ability of a higher
priority interrupt to preempt the execution of a lower priority handler, requires
an interrupt stack (possibly with the support of a interrupt context cache). It is ques-
tionable whether the responsiveness of the nested interrupt technique would override
the increased overhead of saving and restoring many sets of registers.
In the approach shown in the previous code only nine global registers are re-
quired. These serve for all interrupt handlers in the system. During the execution
of the Freeze-mode interrupt handler only four interrupt temporary registers are used
(
it0–it3
).
4.3.13 Making Timer Interrupts Synchronous
The 29K on–chip timer can be configured to generate an interrupt when the
Timer Counter Register (TCR) decrements to zero; more accurately, when the 24–bit
TCV field of the TCV register reaches zero. The TCV field is decremented with each
processor cycle; when it reaches zero, it is loaded with the Timer Reload Value field
(TRV) in the Timer Reload register (TR).
When the Interrupt Enable bit (IE) of the TR register is set and the TCV reaches
zero, the processor will take a timer interrupt unless the DA bit is set in the Configu-
ration Register (CFG). Two–bus and microcontroller members of the 29K family can
additionally disable timer interrupts by setting the TD bits in the CPS register. Timer
interrupts are not disabled by setting the DI bit in the CFG. This means timer inter-
rupts can not be simply disabled along with other external asynchronous interrupts
by setting DI. Note, the TRAP[1,0] asynchronous inputs are not disabled by setting