290
Evaluating and Programming the 29K RISC Family
Bus watching monitors write–through and copy–back of cached data. Memory
regions which are accessed as write–through never have cache blocks which are
modified (that is, their tag M bit is never set). All writes to such regions are performed
to the system memory. Caches with matching blocks will update their data when the
write–through takes place. Only blocks which have been modified get copied back
when the block is reallocated. When a block is copied–back, other caches will retain
their clean copies of the shared data. There will now be no owner of the data. If
another cache performs a load for the data, no processor will intervene and the data
block will be fetched from memory. The data consistency protocol is some times
referred to as a “MOESI” protocol (reflecting the five states: Modified, Owned,
Exclusive, Shared, and Invalid).
The Am29040 processor supports an optimization for use with binary
semaphores. They are frequently used to enable or disable access to shared resources.
A processor can gain exclusive access to a resource via the LOADSET instruction.
The instruction atomically loads the value from the semaphore memory location and
then writes the
set–value
(0xffff,ffff) to the location. The loaded value can then be
tested; if it was already set, access is disallowed. Access to a shared resource is
granted when a zero semaphore is read. The process of accessing the semaphore with
a LOADSET instruction disables allocation of the resource to other requesting
agents. When acquiring unset semaphores, the processor maintains exclusive control
of the system bus.
When access is not granted, a processor will, typically, repeatedly access the
semaphore waiting for it to become unset. However, continually polling a memory
location which is held in shared memory can be a serious performance problem. To
prevent the associated bus activity, the Am29040 can cache binary semaphores. If a
processor
busy–waits
, the semaphore traffic is isolated to the processors data cache.
Additionally, when a semaphore value is found to be set, further LOADSET
instructions are not granted access to the external bus until the semaphore is cleared.
The processor knows the semaphore is set by testing bit–31 of the cached value; in
such case there is no need to perform the SET portion of the LOADSET as the
semaphore is already set. The processor currently holding access to the semaphore
will perform a write broadcast when it releases the shared semaphore. A STOREL
atomic instruction is used to clear the semaphore value. The STOREL instruction,
like a LOADSET to an unset semaphore, has exclusive control of the bus during its
execution. The mechanism ensures that at any time only one processor can gain
access to a shared resource.
5.15 SELECTING AN OPERATING SYSTEM
I am often asked by engineers about to start a 29K project, what they should
look for when selecting an operating system. There are a number of companies
offering operating systems with a range of different capabilities; alternatively a