Chapter 3 Assembly Language Programming
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The original versions of the Am29000 processor (rev–A to rev–B) did not sup-
port byte sized access to external memory. For this reason bytes and half–words had
to be extracted from words after they had been read from memory; the Extract Byte
(EXBYTE) and Extract half–word (EXHW) instructions are supported by the pro-
cessor for just this purpose. Additionally, when data objects smaller than a word were
written to external memory, a read–modify–write process had to be used. The Insert
Byte (INBYTE) and Insert half–word (INHW) instructions supported the process.
Rev–C and later versions of the Am29000 processor and all other 29K family
members directly support byte and half–word accesses to memory. The instructions
described above need no longer be used. To enable current versions of the Am29000
processor to be compatible with the original processor, the DW bit was added to the
processor configuration register (CFG). When the DW bit is clear the processor per-
forms rev–A type memory accesses. All new designs operate with the DW bit set; and
other 29K family members operate with an implied DW bit set.
The OPT field bits specify the size of the data object being moved. They are also
used to indicate a word sized access to Instruction ROM space is requested. External
logic must be incorporated in a memory system design if this option is to be sup-
ported. The OPT field appears on the OPT(2:0) output pins during the memory ac-
cess. It is important that the object size is consistent with the address boundaries de-
fined by the lower bits of the memory address. For example, if a word sized access
(OPT filed value is 0) is attempted with lower address bits aligned to a byte boundary
(A[1:0] not equal 0) then an unaligned access trap may occur. The Unaligned Access
(UA) bit of the Current Processor Status (CPS) register must be set for the trap to be
taken. Additionally, alignment checking is only performed for instruction and data
memory, not for I/O or coprocessor space accesses.
The SB bit is used when reading bytes or half–words from external memory.
Sub–word sized accesses are determined by the OPT field; the processor right–justi-
fies the accessed data within the destination register. The SB bit when set causes the
remainder of the destination to be sign extended with the sign of the loaded data ob-
ject. When SB is clear, the destination register value is zero–extended. The SB bit has
no effect during external memory writes. During write operations, the data object is
replicated in all positions of the data bus. For example, a byte write would result in the
stored byte appearing in all four positions of the stored word. It is the responsibility of
external memory to decode the OPT field and lower address bits when determining
which byte position should be written. Note, the micorcontroller members of the 29K
family implement the memory
glue
logic on–chip.
Instruction field–B (SRCB) supplies the external memory address for LOAD
and STORE instructions. Typically a CONST, or CONST and CONSTH, instruction
sequences precedes the LOAD or STORE instruction and establishes the access ad-
dress for memory. However, the first 256 bytes of memory can be accessed with im-
mediate addressing, where the 8–bit SRCB value contains the address. Some systems