
41
Chapter 1 Architectural Overview
ported. The parallel port, DMA controller, and PIA, also now support transfers lim-
ited to the 16–bit data width.
Generally the number of service support pins such as: programmable Input/Out-
put pins (now 8, 16 for the Am29200 processor); serial communication handshake
signals DTR, DSR; DMA request signals; interrupt request pins; and number of de-
coded PIA and memory banks, have all been reduced. The signal pins supporting vid-
eo–DRAM and burst–mode ROM access have also been omitted. These omissions
do not greatly restrict the suitability of the Am29205 microcontroller for many proj-
ects. The need to make two memory accesses to fetch instructions, which are not sup-
ported by an on–chip cache memory, will result in reduced performance. However,
many embedded systems do not require the full speed performance of a 32–bit RISC
processor.
AMD provides a low cost evaluation board known as the SA29205. The board is
standalone and very like the SA29200 evaluation board; in fact, it will fit with the
same prototype expansion board used by the SA29200. It is provided with a 256k
byte EPROM, organized as 128kx16 bits. The EPROM memory is socket upgradable
to 1M byte. There is 512K byte of 16–bit wide DRAM. For debugging purposes, it
can use the MiniMON29K debug monitor utilizing the on–chip serial port.
1.9
THE Am29240 MICROCONTROLLER
The Am29240 is a follow–on to the Am29200 microcontroller (see Table 1-4).
It was first introduced in 1993. The Am29240 is a member of the Am2924x family
grouping which offers increased on–chip support and greater processing power. In
terms of peripherals the Am29240 has two serial ports in stead of the Am29200’s one.
It also has 4 DMA controllers in stead of two.
Unlike the Am29200, all of the Am29240 DMA channels support queued data
transfer. Additionally, fly–by DMA transfers are optionally supported. Normal
DMA transfers require a read stage followed by a write stage. The data being trans-
ferred is temporarily held in an on–chip buffer after being read. With fly–by DMA the
read and write stages occur at the same time. This results in a faster DMA transfer.
However, the device being accessed must be able to transfer data at the maximum
DRAM access rate.
The Am2924x family grouping, unlike the Am2920x grouping, support virtual
memory addressing. The Translation Look–Aside Buffer (TLB) used to construct an
MMU scheme supports larger page sizes than the Am29000 processor. The page size
can be up to 16M bytes. The large page size enables extensive memory regions to be
mapped with only a few TLB mapping entries. For this reason only 16 TLB entries
are provided (8 sets, two entries per set). A consequence of the relatively large page
size is pages can not be individually protected against Supervisor mode reads and
execution –– this is possible with the smaller pages used by the Am29000 processor
(see section 6.2.1). This loss is outweighed by the benefits of the larger page size