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Chapter 8 Selecting a Processor
performance. Not all of the modeled systems are likely candidates for construction.
They are shown merely to report their relative performance. Some of the most
interesting systems are highlighted. For example, the second from the top entry
shows an Am29205 system with 16–bit 2/2 ROM and 3/2 DRAM. This is an entry
level system. The first entry shows an Am29205 operating from 16–bit DRAM
alone. The notation “*/*” in the ROM/SRAM column indicates that no ROM
memory was used. Such a system would require initialization of the DRAM memory.
This could be achieved with an 8–bit ROM which transferred its contents to DRAM
before application code execution commenced. Note, it is not possible to build a
DRAM–only system where a dual–ported DRAM is initialized by another processor.
This is because after reset, program execution commences from ROM region 0. This
does mean an SRAM–only system could be constructed; assuming that the SRAM is
located in ROM region 0, and is somehow initialized before processor reset.
The second entry, the 2/2–3/2 system, was linked such that instructions were
fetched from the 2/2 ROM space; all data was accessed from the 3/2 DRAM. The
combined ROM–DRAM system is faster than the 3/2 DRAM–only system. The
DRAM–only system has 81% of the faster system’s performance. This is due to
instruction accesses being directed to the faster 2/2 memory and the frequent
occurrence of DRAM precharge cycles. The Am29200 DRAM is frequently referred
to as 3/2, this assumes the 1–cycle of RAS–precharge is hidden. When DRAM–only
systems are used, the precharge is not likely to be hidden, and the access is truly 4/2
rather than 3/2. This is explained in section 1.14.1 under the
Am29200 and Am29205
subheading. Given that even inexpensive EPROM devices can be 1.5 to 2–times the
cost of DRAM (per byte), it is less expensive to use a single 8–bit EPROM to
initialize the DRAM, and then execute the program from DRAM. However, there is a
loss of performance with this technique.
The sixth entry shows an Am29205 system with 1/1 ROM and 3/2 DRAM. The
system has substantially increased performance over the 2/2 ROM system (66%
faster). The notation 1/1 is used here to indicate instruction read access times only.
The microcontroller family requires one wait state when writing to ROM space. This
results in a minimum write access time of 2–cycles for ROM space. Although this is
important to note, it has no impact here as the system performs all data writes to
DRAM. However, the system is unbuildable due to the unavailability of ROM
devices which can deal with the very fast access times.
The access times for ROM space are determined by three parameters. First, the
period of the memory system clock (CP) –– all memory accesses are synchronized to
the system clock. Second, the delay before synchronous outputs become valid (OV).
Third, the input setup time (IS) for synchronous input signals. When performing
single–cycle memory access, the access time is determined from the ROMOE signal
becoming valid after the falling edge of MEMCLCK (OV
F
). When wait states (WS)
are used, the access time is determined from the address outputs becoming valid after