
50
Evaluating and Programming the 29K RISC Family
move–to special register instructions are among a small group of instructions which
cause processor serialization. That is, all outstanding operations, such as overlapping
load or store instructions, are completed before the serializing instruction com-
mences.
Special register space is divided into two regions (see Figure 1-15). Those reg-
isters whose address is below
sr128
can only be accessed by the processor operating
in Supervisor mode. Different members of the 29K family have extensions to the
global registers shown in Figure 1-15. However, special registers
sr0–sr14
are a sub-
set which appear in all family members. Certain, generally lower cost, family mem-
bers such as the Am29005 processor, which have no memory management unit, do
not have the relevant MMU support registers (
sr13
and
sr14
). I shall first describe the
restricted access, or protected, special registers. I shall not go into the exact bit–field
operations in detail, for an expansion of field meanings see later chapters or the rele-
vant processor User’s Manual. The objective here is to provide a framework for bet-
ter understanding the special register space.
Special registers are not generally known by their special register number. For
example, the program counter buffer register PC1 is known as PC1 by assembly lan-
guage programming tools rather than
sr11
.
Vector Area Base
Special register
sr0
, better known as VAB, is a pointer to the base of a table of
256 address values. Each interrupt or trap is assigned a unique vector number. Vector
numbers 0–63 are assigned to specific processor support tasks. When an interrupt or
trap exception is taken, the vector number is used to index the table of address values.
The identified address value is read and used as the start address of the exception
handling routine. Alternatively with 3–bus members of the 29K family, the vector
table can contain 256 blocks of instructions. The VF bit (vector fetch) in the proces-
sor Configuration register (CFG) is used to select the vector table configuration.
Each block is limited to 64 instructions, but via this method the interrupt handler can
be reached faster as the start of, say, an interrupt handler need not be preceded by a
fetch of the address of the handler. In practice the table of vectors to handlers, rather
than handlers themselves, is predominantly used due to the more efficient use of
memory. For this reason the two later 2–bus members of the 29K family only support
the table of vectors method; and the VF bit in the CFG register is reserved and effec-
tively set.
The first 29K processor, the Am29000, has a VAB register which requires the
base of the vector table to be aligned to a 64k byte address boundary. This can be in-
convenient and lead to memory wastage. More recent family members provide for a
1k byte boundary. Because the 3–bus family members support instructions being lo-
cated in Instruction space and ROM space (memory space is described in section
1.10.4), it is possible with these processors to specify that handler routines are in
ROM space by setting the RV bit (ROM vector area) in the CFG register when the VF