October 13 1995, Draft 1
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Chapter 7 Software Debugging
Logic Analyzer Connection
Many of the evaluation boards offered by AMD contain sockets suitable for
quick connection of a Hewlett–Packard logic analyzer. This simplifies the process of
connecting the analyzer to the processor’s signal pins. Certain other logic analyzer
manufacturers support a compatible termination adapter (pod) format. Logic analyz-
ers such as the HP16500B (system) and the HP166x series connect directly to the
evaluation board connectors. This is convenient, as connecting to devices in pack-
ages other than PGA can be cumbersome and unreliable. Connection to your own
board can be achieved via a logic analyzer preprocessor: a preprocessor consist of a
small circuit board which connects directly into the processor socket (possibly with
the aid of a socket extender). A replacement processor is located on the board along
with an array of analyzer connection sockets. Corelis Inc. supply preprocessors for
microprocessors and microcontrollers in the 29K family.
Microcontroller members of the 29K family incorporate on–chip memory inter-
face controllers. This results in the microcontroller providing RAS and CAS address
information separately (multiplexed on the same address pins) rather than a complete
DRAM address value. Consequently, it is necessary to latch the RAS address in-
formation and later combine the CAS address bits to produce a complete DRAM ad-
dress. If the address latching technique is not used, then the logic analyzer can not
display the complete address used for a DRAM access. This is very inconvenient. For
this reason, AMD provide address latching circuitry on their more recent microcon-
troller evaluation boards. Corelis also provide address latches on their preprocessors.
The active components on the preprocessor draw power from the pins supplying
power to the processor.
A Logic Analyzer as a Software Development Tool
Logic analyzers can be used to study a circuit’s state and timing information.
Hardware engineers typically display state information in hexadecimal or binary
format (see Figure 7-14). Software developers need a format which is more relevant
to their task. To this end, Corelis provide a tool which runs on the logic analyzer and
enables the processor bus signals to be displayed in assembly instruction format. The
tool is used in conjunction with a configuration file which formats the analyzer to the
assigned preprocessor signals. (For example, file POD_040._D for the Am29040
preprocessor.) When the configuration file is used, the task of first assigning labels to
the termination connector signals is eliminated. When the inverse assembler tool is
used, the DATA label shown on Figure 7-14 can optionally be displayed in terms of
29K assembly instructions rather than the hexadecimal equivalent.