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參數(shù)資料
| 型號： | TMS34020 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | GRAPHICS PROCESSORS |
| 中文描述： | 圖形處理器 |
| 文件頁數(shù)： | 9/82頁 |
| 文件大小： | 1359K |
| 代理商： | TMS34020 |
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TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
9
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
functional block diagram
HA5–HA31
HBS0–HBS3
HCS
HREAD
HWRITE
HINT
HRDY
HDST
HOE
GI
R0
R1
EMU0
EMU1
EMU2
EMU3
CLKIN
LCLK1
LCLK2
RESET, LINT1,
LINT2
LAD0 – LAD31
RCA0–RCA12
DDIN
DDOUT
RAS
CAS0 – CAS3
WE
TR/QE
ALTCH
SF
PGMD
SIZE16
LRDY
BUSFLT
CAMD
VSYNC
HSYNC
CSYNC/HBLNK
CBLNK/VBLNK
VCLK
SCLK
27
13
Host
Address
Latch
Host
Interface
Multi-
Processor
Interface
Emulation
Interface
System
Clocks
Buffer/
Page-mode
Register
MUX
Bus
Control
DRAM/
VRAM
Interface
Bus
Interface
Video
Timing
and
Control
Local
Memory
and
Bus
Timing
I/O
Regs
LRU
ALU
Barrel
Shifter
Microcontrol ROM
Reset and Interrupts
Cache
PC
ST
Register
File A
Register
File B
SP
Decode
4
4
32
3
architecture (continued)
register files
Boolean, arithmetic, pixel-processing, byte, and field-move instructions operate on data within the
general-purpose register files. The TMS34020 contains two register files of fifteen 32-bit registers and a system
stack pointer (SP). The SP is addressed in both register file A and register file B as a sixteenth register. Transfers
between registers and memory are facilitated via a complete set of field-move instructions with selectable field
sizes.
The 15 general-purpose registers in register file A are used for high-level language support and
assembly-language programming. The 15 registers in register file B are dedicated to special functions during
PixBlts and other pixel operations but can be used as general-purpose registers at other times.
stack pointer (SP)
The stack pointer is a dedicated 32-bit internal register that points to the top of the system stack.
program counter (PC)
The TMS34020’s 32-bit program counter register points to the next instruction-stream word to be fetched. Since
instruction words are aligned to 16-bit boundaries, the four LSBs of the PC are always zero.
instruction cache
An on-chip cache contains 512 bytes of RAM and provides unimpeded access to instructions. The cache
operates automatically and is transparent to software. The cache is divided into four 128-byte segments.
Associated with each segment is a 22-bit segment start address register (SSA) to identify the addresses in
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