- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385001 > TMS34020 (Texas Instruments, Inc.) GRAPHICS PROCESSORS PDF資料下載
參數(shù)資料
| 型號： | TMS34020 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | GRAPHICS PROCESSORS |
| 中文描述： | 圖形處理器 |
| 文件頁數(shù)： | 19/82頁 |
| 文件大?。?/td> | 1359K |
| 代理商： | TMS34020 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁當前第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
19
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
special 1M VRAM cycles
The TMS34020 provides control for special-function VRAM cycles that are available in the 1M devices. These
cycles are obtained by the appropriate timing control of the SF, CAS, TR/QE, and WE pins of the VRAMs at the
falling edge of RAS. The cycles include:
Load write mask.
Load color mask.
Block write (no mask).
Block write (current mask).
Write using mask.
Alternate write transfer.
In addition, other special modes can be implemented by using external logic.
multiprocessor arbitration
The multiprocessor interface allows multiple processors to operate in a system sharing the same local memory.
The use of the grant in (GI) and the priority request signals (R0 and R1) allows a flexible method of passing
control from one processor to another. The control scheme allows local memory cycles to occur back-to-back,
even when passing control from on TMS34020 to another. Synchronization of multiple TMS34020s in a system
occurs at reset with the rising edge of RESET meeting the setup and hold requirements to CLKIN, so all
TMS34020s are certain to respond to the RESET during the same quarter cycle. RESET is not required to be
synchronous to CLKIN, except to allow synchronization of multiple TMS34020s in a system.
The GI priority for multiprocessing environments is determined by arbitration logic external to the TMS34020.
If GI goes inactive (high), the TMS34020 releases the bus on the next available cycle boundary. If the cycle in
progress has not successfully completed, the TMS34020 restarts the cycle upon regaining control of the bus.
Normally, if the TMS34020 asserts both R0 and R1 low, it should be given the control of the bus by the arbitrator.
host interface
The TMS34020 host interface allows the local memory to be mapped into the host address space. The
TMS34020 acts as a DRAM controller for the host. The address for the host access is latched within the
TMS34020; however, the data for the access is transferred via external transceivers. The host selects the
address of a 32-bit long word for an access using the 27 host-address lines, HA5–HA31. If the host desires byte
addressability, it can select the active bytes for the access by using HBS0–HBS3. The TMS34020 always reads
32 bits from memory; however, on host writes, it uses the host byte selects to enable CAS0–CAS3 to memory.
The address and byte selects are latched at the falling edge of HCS within the TMS34020. The host indicates
a read or write by asserting HREAD or HWRITE (as appropriate) either before or after HCS. HREAD and
HWRITE must never be asserted at the same time.
The TMS34020 responds to a host-read request by latching the requested data in the external latches and
providing HRDY to the host, indicating that the read cycle is completing. The rising edge of HDST with HRDY
high indicates data is latched in the external transceivers.
The host indicates that a write to a particular location is required by providing the address and asserting the
HWRITE signal. The host must maintain both HCS and HWRITE asserted until valid data is in the transceivers.
(The rising edge of HOE with HRDY high indicates that the data previously stored in the external transceivers
has been written to memory.) Typically, the rising edge of HWRITE is used to strobe the data into the latches
and signal the TMS34020 that the write access can start. The TMS34020 uses its byte-write capability to write
only to the selected bytes.
相關PDF資料 |
PDF描述 |
|---|---|
| TMS3450NL | LED DUPLEX DIGITAL RADIO CLOCK |
| TMS3471CFS | 780- 】 488-pixel ccd image sensor |
| TMS3471 | 2/3-INCH NTSC TIMER |
| TMS3473 | PARALLEL DRIVER |
| TMS370C036A | 8-BIT MICROCONTROLLER |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TMS3450NL | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TMS3459BNL | 制造商:Panasonic Industrial Company 功能描述:IC |
| TMS3471C | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TMS3472ADW | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TMS3637D | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復。