
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
54
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
signal transition levels
2 V
0.8 V
Figure 30. TTL-Level Inputs
For a high-to-low transition on a TTL-compatible input signal, the level at which the input is said to be no longer
high is 2 V, and the level at which the input is said to be low is 0.8 V. For a low-to-high transition, the level at which
the input is said to be no longer low is 0.8 V, and the level at which the input is said to be high is
2 V.
2.6 V
2 V
0.8 V
0.6 V
Figure 31. TTL-Level Outputs
TTL-level outputs are driven to a minimum logic-high level of 2.6 V and to a maximum logic-low level of 0.6 V.
For a high-to-low transition on a TTL-compatible output signal, the level at which the output is said to be no longer
high is 2 V, and the level at which the output is said to be low is 0.8 V. For a low-to-high transition, the level at
which the output is said to be no longer low is 0.8 V, and the level at which the output is said to be high is 2 V.
Timing parameters 12a and 13a do not follow these conventions. They are measured at a 1.5-V level.
test measurement
The test load circuit shown in Figure 32 represents the programmable load of the tester pin electronics, which
are used to verify timing parameters of TMS34020 output signals.
IOL
VLOAD
IOH
CLOAD
Test
Point
From Output
Under Test
Where:
IOL = 2 mA (all outputs)
IOH = 400
μ
A (all outputs)
VLOAD = 1.5 V
CLOAD = 65 pF typical load circuit distributed capacitance
Figure 32. Test Load Circuit