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| 型號： | TMS34020 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | GRAPHICS PROCESSORS |
| 中文描述： | 圖形處理器 |
| 文件頁數(shù)： | 44/82頁 |
| 文件大小： | 1359K |
| 代理商： | TMS34020 |
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TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
44
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Q4
Q1
Q2
Q3
Q4*
Q1
Q2
Q3
Q4
Q1
Row
Column
Previous Read
1st Read Valid
1st Address
Row
Column
2nd Address
Q2
Q3
Q4*
Q1
Q2
Q3
Q4
Q1
2nd
Local-Memory Host Read Cycle
Local-Memory Host Prefetch Cycle
HA/HBS
HCS
HREAD
HWRITE
HRDY
HOE
HDST
LAD
GI
CAMD
RCA
SF
ALTCH
RAS
CAS
WE
TR/QE
DDIN
DDOUT
LRDY
SIZE16
PGMD
BUSERR
R0
R1
DATA
(out)
*See clock stretch, page 21.
Figure 21. Back-to-Back Host Read Cycles With Implicit Addressing; HREAD as Strobe
The host-access request is synchronized to the TMS34020 at the beginning of Q4 so that the local memory cycle
may begin in Q1.
In block mode (prefetch after read), the TMS34020 automatically initiates sequential read accesses as soon
as the host deasserts the current read request. In this example, the host reads a location and must wait for the
first access to complete. When the host removes HREAD, indicating the end of the first read, the TMS34020
starts to prefetch the next sequential location. When the host makes the next request, the TMS34020 has
prefetched the data so that the host reads with no delay. While in block mode, the TMS34020 continues to
prefetch data for the host read each time the host removes either HREAD or HCS. If the address present and
latched at the falling edge of HCS matches the previously prefetched address, the HRDY signal is asserted high
so that the host can read with no delay.
In read/modify/write mode (prefetch after write), the TMS34020 initiates the read access as soon as the current
write request is deasserted.
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