參數(shù)資料
型號(hào)： TMS34020
廠商： Texas Instruments, Inc.
英文描述： GRAPHICS PROCESSORS
中文描述： 圖形處理器
文件頁數(shù)： 30/82頁
文件大?。?/td> 1359K
代理商： TMS34020
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
30
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Row
Column (S=0)
Column (S=1)
Q4
Q1
Q2
Q3
Q4*
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Low Address
Address Subcycle
Data Transfer
Subcycle
Data Transfer
Subcycle
High Address
Hi
Low
LCLCK1
LCLCK2
GI
LAD0–LAD15
LAD16–LAD31
CAMD
RCA
ALTCH
RAS
CAS0
CAS1
CAS2
CAS3
WE
TR/QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
*See clock stretch, page 21.
NOTE A: RCA0 may be used to determine accesses to odd or even words because it outputs the least significant bit of the word address during
the column-address time (except in 4M-mode with CAMD = 1).
Figure 7. Dynamic Bus Sizing, Read Cycle
When SIZE16 is selected low, the TMS34020 performs a second cycle to read (or write) the remaining 16 bits
of the word. Reads always access all 32 bits (all CAS strobes are active). Internally, the TMS34020 latches both
the high and the low words obtained on the first read cycle. The sense of SIZE16 on the second (odd-word)
access is used to determine which half of the bus is to be sampled to replace the data word latched during the
first cycle.
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