參數(shù)資料
型號： TMS34020
廠商： Texas Instruments, Inc.
英文描述： GRAPHICS PROCESSORS
中文描述： 圖形處理器
文件頁數(shù)： 77/82頁
文件大?。?/td> 1359K
代理商： TMS34020
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
77
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
video interface timing: external sync inputs (see Note 7)
NO.
PARAMETER
’34020-32
’34020A-32
’34020A-40
UNIT
MIN
20
MAX
MIN
20
MAX
131
tsu(SL-VCK
↑
)
tsu(SH-VCK
↑
)
th(VCKH-SV)
Setup time, HSYNC, VSYNC, CSYNC low to VCLK
↑
Setup time, HSYNC, VSYNC, CSYNC high to VCLK
↑
ns
132
20
20
ns
133
Hold time, HSYNC, VSYNC, CSYNC valid after VCLK high
20
20
ns
NOTE 7: Setup and hold times on asynchronous inputs are required only to assure recognition at indicated clock edges.
(see Note B)
(see Note A)
D
C
B
A
HSYNC
VSYNC
CSYNC
(INPUTS)
VCLK
132
133
131
133
NOTES: A. If the falling edge of the sync signal occurs more than th(VCKH-SV) after VCLK edge A and at least tsu(SL-VCKH
↑
) before edge B, the
transition will be detected at edge B instead of edge A.
B. If the rising edge of the sync signal occurs more than th(VCKH-SV) after VCLK edge C and at least tsu(SH-VCKH
↑
) before edge D, the
transition will be detected at edge D instead of edge C.
Figure 48. Video Interface Timing: External Sync Inputs
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