參數(shù)資料
型號(hào)： TMS34020
廠商： Texas Instruments, Inc.
英文描述： GRAPHICS PROCESSORS
中文描述： 圖形處理器
文件頁(yè)數(shù)： 22/82頁(yè)
文件大?。?/td> 1359K
代理商： TMS34020
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
22
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
enabling clock stretch
Clock-stretch mode is enabled and disabled via a bit in the CONFIG register (C00001A0h).
0
1
2
3
4
5
6
7
C
S
E
Loaded at Reset from Reset Vector
Protected Byte
CONFIG register C00001A0h
0: Disable stretch mode (normal operation)
1: Enable stretch mode
CSE=
CSE=
31
Bit 4 of the CONFIG register is the clock-stretch-enable mode bit. A 0 in this bit will disable stretch mode and
a 1 in this bit will enable stretch mode. The bit is cleared during reset; i.e., stretch mode is disabled by default.
When stretch mode is enabled, the following machine cycles are stretched:
1.
2.
All address cycles of all memory access sequences.
Read data cycles in read-modify-write sequences.
Notes:
a)
The host default cycle shown on page 8-49 of the TMS34020 User’s Guideis not stretched because
it is not a true address cycle; i.e., RAS, etc., do not go low.
b)
The CPU default cycle, which is similar to the host default cycle in that RAS, etc., do not go low, is
also not stretched.
c)
Clock-stretch mode disregards the page-mode input, so that read data cycles in nonpage-mode
read-modify-write sequences are stretched, even though there are no timing constraints that re-
quire a stretch.
d)
All other memory subcycles are notstretched, even if the TMS34020A is running with the CSE bit
set to 1.
The advantage of this implementation of clock-stretch mode is that the TMS34020A can execute code at
maximum speed, slowing down only during certain parts of memory access sequences.
It is important to remember that a stretched cycle is 25% longer than a normal cycle, and that the TMS34020A
(with the exception of the video logic, which is clocked independently by VCLK) will effectively slow down during
such a stretched cycle.
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