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參數(shù)資料
| 型號： | TMS34020 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | GRAPHICS PROCESSORS |
| 中文描述： | 圖形處理器 |
| 文件頁數(shù)： | 12/82頁 |
| 文件大?。?/td> | 1359K |
| 代理商： | TMS34020 |
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TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
12
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
The TMS34020 supports various display resolutions and either interlaced or noninterlaced video. The
TMS34020 can optionally be programmed to synchronize to externally generated sync signals so that images
created by the TMS34020 may be superimposed upon images created externally. The external sync mode can
also be used to synchronize the video signals generated by two or more TMS34020s in a multiple-TMS34020
graphics system.
CPU control registers
Five of the I/O registers (CONVDP, CONVMP, CONVSP, CONTROL, and PSIZE) provide CPU control to
configure the TMS34020 for operation with specific characteristics. These characteristics include pitches for
pixel transfers, window-checking mode, Boolean or arithmetic pixel-processing operation, transparency mode,
PixBlt direction control, and pixel size.
interrupt interface registers
Two dedicated I/O registers (INTENB and INTPEND) monitor and mask interrupt requests to the TMS34020,
including two externally generated interrupts and three internally generated interrupts. An internal interrupt
request can be generated on one of the following conditions.
Window violation: an attempt has been made to write a pixel to a location inside or outside a specified
window boundary.
Host interrupt: the host processor has set the interrupt-request bit in the host control register.
Display interrupt: a specified horizontal line in the frame has been displayed on the screen.
Bus fault.
Single-step emulator.
A nonmaskable interrupt occurs when the host processor sets a control bit in the host interface register (NMI
in HSTCTLH). The host-initiated interrupt is associated with a mode bit (NMIM in HSTCTLH) that enables and
disables saving of the processor state on the stack when the interrupt occurs. This is useful if the host wishes
to use the host interrupt before releasing the TMS34020 to execute instructions (i.e., before the stack pointer
is initialized). The TMS34020 reset function is controlled by a dedicated pin.
memory controller/local memory interface
The memory controller manages the TMS34020’s interface to the local memory and automatically performs the
bit alignment and masking necessary to access data located at arbitrary bit boundaries within memory. The
memory controller operates autonomously with respect to the CPU. It has a write queue one field (1 to 32 bits)
deep that permits it to complete the memory cycles necessary to insert a field into memory without delaying the
execution of subsequent instructions. Only when a second memory operation is required before completion of
the first operation is the TMS34020 forced to defer execution of the subsequent instruction.
The TMS34020 directly interfaces to standard dynamic RAMs and, in particular, to standard video RAMs such
as the TMS44C251 multiport VRAMs. The TMS34020 memory interface consists of the local address/data bus
(LAD), the DRAM row/column address (RCA) bus, and associated control signals. The currently selected word
address (28 bits) and status (4 bits) are multiplexed with data on the LAD bus. The RCA bus allows direct
connection to address/address multiplexed DRAMs from 64K to 16M. Refresh for DRAMs is supported by
CAS-before-RAS refresh cycles.
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