
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
63
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
host interface timing (block read cycle) (see Figure 38 and Note 3)
NO.
PARAMETER
’34020-32
’34020A-32
’34020A-40
UNIT
MIN
MAX
MIN
MAX
37
tsu(RDH-CK2
↓
)
Setup time, HREAD high to LCLK2
↓
, prefetch read
mode
30
25
ns
39
td(CK1
↑
-RYH)
Delay time from LCLK1
↑
to HRDY high
tQ+20
tQ+18
ns
40
td(RDH-RYL)
Delay time from earlier of HREAD or HCS high to
HRDY low
20
18
ns
41
td(CK2
↓
-STL)
td(CK1
↓
-STH)
tsu(STL-RY
↑
)
td(RY
↑
-STH)
Delay time from LCLK2
↓
to HDST low
Delay time from LCLK1
↓
to HDST high
Setup time of HDST low to HRDY
↑
Delay time from HRDY
↑
to HDST high
tQ+15+ s
tQ+15
tQ+13.5+ s
tQ+13.5
ns
42
ns
43
tQ– 15
tQ–13.5
ns
44
2tQ+15
2tQ+13.5
ns
45
td(RDL-RYH)
Delay time from later of HREAD or HCS low to HRDY
high after prefetch
25
20
ns
Setup time to insure recognition of input on this clock edge. When the TMS34020 is set for block reads, the deassertion of HREAD is used to
request a local memory cycle at the next sequential address location.
NOTE 3. Although HCS, HREAD, and HWRITE can be totally asynchronous to the TMS34020, cycle responses to the signals are determined
by local memory cycles.
HDST
HRDY
HREAD
HCS
LCLK2
LCLK1
43
40
37
42
26
39
Q4*
Q1
Q2
Q3
Q4*
Q1
Q2
Q3
Q4*
Q1
Q2
Q3
Q4*
45
41
44
40
26
37
30
*See clock stretch, page 21.
Figure 38. Host Interface Timing (Block Read Cycle)