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參數(shù)資料
| 型號： | TMS34020 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | GRAPHICS PROCESSORS |
| 中文描述： | 圖形處理器 |
| 文件頁數(shù)： | 14/82頁 |
| 文件大?。?/td> | 1359K |
| 代理商： | TMS34020 |
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TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
14
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
At the time the TMS34020 fetches the level-0 vector address (the reset vector), the least significant four bits
(bit-address part) are used to load configuration data that establishes the initial condition of the big endian/little
endianmode and the current RCA bus configuration bits in the CONFIG register as described in the I/O register
section.
Unlike other interrupts and software traps, reset does not save the previous ST or PC values (this can also occur
on host-initiated nonmaskable interrupts if the NMIM bit in HSTCTLH is set to a 1), since the value of the stack
pointer just before a reset is generally not valid, and saving these values on the stack could contaminate valid
memory locations. A TRAP 0 instruction, which uses the same vector address as reset, similarly does not save
the ST or PC values.
asserting reset
A reset is initiated by asserting the RESET input pin to its active-low level. To reset the TMS34020 at power up,
RESET must remain low for a minimum of 40 local clock periods (LCLK1 and LCLK2) after power levels have
become stable. At times other than power up, the TMS34020 may be reset by holding RESET low for a minimum
of four local clock periods; the GSP will enter an internal reset state for 34 local clock cycles. While in the internal
reset state and RESET is high, memory refresh cycles occur.
reset and multiprocessor synchronization
The synchronization of multiple TMS34020s sharing a local memory is done using the RESET input. In systems
where the multiprocessor interface is used to control the access to a common memory, the processors must
be synchronized. Synchronization is achieved by taking RESET high within a specific interval relative to CLKIN.
This may be done by using CLKIN to clock RESET as received by the TMS34020s. All TMS34020s to be
synchronized should use the same CLKIN and RESET inputs. All of the local memory and bus control signals
should be connected in parallel (without buffers) between the processors. After power up, the processors are
not necessarily synchronized with respect to the particular quarter cycle in progress. The rising edge of RESET
is used to set the TMS34020 to a particular quarter cycle by adding Q1 cycles. All TMS34020s in a
multiprocessor environment operate on the same quarter cycle within 10 quarter cycles after the rising edge
of RESET.
reset and DRAM/VRAM initialization
The TMS34020 drives its RAS signal inactive (high) as long as RESET remains low. The specifications for
certain DRAM and VRAM devices require that the RAS signal be driven inactive for 1 millisecond after power
is stable to provide the proper conditions for the DRAMs. Typically, eight RAS cycles are also required to initialize
the DRAMs for proper operation. In general, holding RESET low for tmicroseconds ensures that RAS remains
high initially for t–(10t
Q
)microseconds. The TMS34020 memory controller automatically inserts the required
eight RAS cycles after all resets (after power up or after the internal reset state) by issuing CAS-before-RAS
refresh cycles before it allows the CPU access to memory. A host must delay requests to memory until the
initialization cycles have had sufficient time to complete. Immediately following reset, the TMS34020 is set to
perform a refresh sequence every eight cycles.
At times other than power up, to maintain the memory in DRAMs and do a reset, the RESET pulse must not
exceed the maximum refresh interval of the DRAMs minus the time for the TMS34020 to refresh the memories.
On reset, the TMS34020 is set to do a refresh cycle every eight local clock periods. A 32-MHz (CLKIN) system
with one (refresh) bank of D/VRAM would be completely refreshed in one-sixteenth of the total memory refresh
interval. The reset pulse then should not exceed about fifteen-sixteenths of the total refresh interval required
by the DRAMs to maintain memory integrity.
If the RESET signal remains low longer than the maximum refresh interval specified for the memory, the
previous contents of the local memory may not be valid after the reset.
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