參數(shù)資料
型號： TMS34020
廠商： Texas Instruments, Inc.
英文描述： GRAPHICS PROCESSORS
中文描述： 圖形處理器
文件頁數(shù)： 15/82頁
文件大小： 1359K
代理商： TMS34020
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
15
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
initial state following reset
While the RESET pin is asserted low (or while in the internal reset state), the TMS34020’s output and
bidirectional pins are forced to the states below.
INITIAL STATE OF PINS FOLLOWING A RESET (WITH GI LOW)
OUTPUTS DRIVEN HIGH
OUTPUTS DRIVEN LOW
BIDIRECTIONAL DRIVEN TO
HIGH-IMPEDANCE
RAS
HRDY
VSYNC
CAS0–CAS3
CBLNK/VBLNK
HSYNC
WE
DDIN
CSYNC/HBLNK
TR/QE
LAD0–LAD31
DDOUT
ALTCH
HINT
R0
R1
HOE
HDST
EMU3
RCA0–RCA12
SF
NOTE: If GI is high, then all GI-controlled pins will be in the high-impedance state. The GI-controlled pins are RAS, CAS0–CAS3, WE, TR/QE,
DDOUT, DDIN, ALTCH, HOE, HDST, RCA0–RCA12, LAD0–LAD31, and SF.
Immediately following reset, all I/O registers are cleared (set to 0000), with the exception of the HLT bit in the
HSTCTLH register. The HLT bit is set to 1 if the HCS pin is high just prior to the low-to-high transition of RESET;
otherwise, it is set to 0.
Just prior to the execution of the first instruction in the reset routine, the TMS34020’s internal registers are in
the following states:
General-purpose register files A and B are uninitialized.
The ST is set to 0000 0010h.
The PC contains the most significant 28 bits of the vector fetched from memory address FFFF FFE0h
(the least significant four bits of the PC are set to zero).
The BEN bit in the I/O register CONFIG is set to the least significant bit read from the vector fetched from
memory address FFFF FFE0h.
The CBP, RCM0, and RCM1 bits in the I/O register CONFIG are set to the corresponding bits read from
the vector fetched from memory address FFFF FFE0h. The configuration-byte-protect bit (CBP) can be
set high to prevent further modification of the lower eight bits of the I/O register CONFIG.
The state of the instruction cache at this time is as follows:
The SSA (segment start address) registers are uninitialized.
The LRU (least-recently-used) stack is set to the initial sequence 0, 1, 2, 3, where 0 occupies the
most-recently-used position and 3 occupies the least-recently-used position.
All P (present) flags are cleared to 0s.
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