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參數(shù)資料
| 型號： | TMS34020 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | GRAPHICS PROCESSORS |
| 中文描述： | 圖形處理器 |
| 文件頁數(shù)： | 16/82頁 |
| 文件大小： | 1359K |
| 代理商： | TMS34020 |
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TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
16
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
local memory and DRAM/VRAM interface
The TMS34020 local memory interface consists of an address/data multiplexed bus on which address and data
are transmitted. The associated control signals support memory widths of 16 or 32 bits, burst (page-mode)
accesses, local-memory wait states, and optional external data bus buffers. The TMS34020 DRAM/VRAM
interface consists of an address/address multiplexed bus and the control signals to interface directly to both
DRAMs and VRAMs. The local-memory interface and the DRAM/VRAM interface are interrelated and therefore
considered together for this description. At the beginning of a typical memory cycle, the address and status of
the current cycle are output on the LAD bus, while the row address is output on the row/column address (RCA)
bus. ALTCH and RAS are used to latch the address/status and row address, respectively, on these two buses.
The LAD bus is then used to transfer data to or from the memory while the RCA bus is set to the column address
for the memory. LAD31 is the most significant bit of the address or data.
LAD During the Address Cycle
W
31
5
4
3
0
ADDRESS
STS
ADDRESS
W = 0
W = 1
STS
— Memory address (select for 128M 32-bit long words)
— Access to lower 16-bit word (even-addressed word or 32-bit boundary)
— Access to upper 16-bit word (odd-addressed word)
— Bus cycle status code
The address output on the row/column address (RCA) lines is determined by the row/column mode bits (RCM0
and RCM1 in the I/O register CONFIG) and the state of the column address mode pin (CAMD) during each
memory cycle. The CAMD signal is sampled on the internal Q4 clock phase, which allows CAMD to be
generated by static logic wired to the local address/data (LAD) bus.
BASIC MEMORY ROW/COLUMN ACCESS MODES
RCM1
RCM0
VRAM MODE
64K
×
N
256K
×
N
1M
×
N
4M
×
N
ADDRS
BANKS
CAMD SUPPORT MATRICES
0
0
8
16
64K
×
16, 64K
×
32, 256K
×
16, 256K
×
32, 1M
×
16, 1M
×
32
2564K
×
16, 256K
×
32, 1M
×
16, 1M
×
32, 4M
×
32
1M
×
16, 1M
×
32, 4M
×
16, 4M
×
32
4M
×
16, 4M
×
32, 16M
×
32
0
1
9
8
1
0
10
4
1
1
11
2
VRAM Mode = basic size of VRAM addressing supported with CAMD = 0.
Addrs = number of RCA signals required to provide row/column addressing.
Banks = number of possible interleaved 32-bit wide memory spaces.
CAMD Support = possible sizes and configurations of DRAMs that may be supported within the basic VRAM mode.
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