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參數(shù)資料
| 型號： | TMS34020 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | GRAPHICS PROCESSORS |
| 中文描述： | 圖形處理器 |
| 文件頁數(shù)： | 50/82頁 |
| 文件大?。?/td> | 1359K |
| 代理商： | TMS34020 |
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TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
50
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
GI
LAD
Command
Address
ALTCH
RAS
WE
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
R1
Q2
Q3
Q4*
Q1
CAMD
CAS
TR/QE
SF
DDIN
DDOUT
R0
Data 1
PGMD
SIZE16
LRDY
BUSFLT
RCA
LAD
Data 2
2nd Column
1st Column
Row
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
LCLK1
LCLK2
(TMS34020)
(memory)
Command Cycle
Address
Data Tansfer
Data Transfer
*See clock stretch, page 21.
NOTES: A. LAD (TMS34020):
LAD (memory):
Command:
Address:
Data n:
Output to the LAD bus by the TMS34020
Output to the LAD bus by the memory
Coprocessor ID, instruction and status code present on LAD
Memory address for the data transfer, with coprocessor status code
Data to or from the coprocessor (number of values transferred depends on a value in a register or count in
the instruction)
B. All coprocessor cycles are implemented as 32-bit operations; therefore SIZE16 should be high during these cycles.
Figure 27. Transfer Memory to Coprocessor Register(s)
Data transfer from memory to a coprocessor requires an initialization cycle to inform the coprocessor what is
to be transferred and then a memory cycle to perform the actual transfer. The coprocessor can place status
information on the LAD bus during the initialization cycle for the TMS34020. Two types of
memory-to-coprocessor instructions are supported: one provides a count (from 1 to 32) of data to be moved
in the instruction; the other specifies a register in the TMS34020 to be used for the count. Both instructions
specify a register to be used as an index into memory. The index may be post-incremented or pre-decremented
on each transfer cycle.
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