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| 型號： | TMS34020 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | GRAPHICS PROCESSORS |
| 中文描述： | 圖形處理器 |
| 文件頁數(shù)： | 6/82頁 |
| 文件大小： | 1359K |
| 代理商： | TMS34020 |
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TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
6
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Terminal Functions (Continued)
NAME
I/O
DESCRIPTION
HOST INTERFACE
HA5–HA31
I
27 host-address input signals.
A host can access a long word by placing the address on these lines. HA5–HA31
correspond to the LAD5–LAD31 signals that output the address to the local memory.
HBS0–HBS3
I
4 host byte selects.
The byte selects identify which bytes within the long word are being selected.
HCS
I
Host chip select.
A host drives this signal low to latch the current host address present on HA5–HA31 and the host
byte selects on HBS0–HBS3. This signal also enables host access cycles to the TMS34020 I/O registers or local
memory. During the low-to-high transition of RESET, the level on the HCS input determines whether the TMS34020
is halted (HCS is high for host-present mode) or whether it begins executing its reset service routine (HCS is low
for self-bootstrap mode).
HDST
O
Host data-latch strobe.
The rising edge of this signal latches data from the TMS34020 local address space to the
external host data latch on host read accesses. It can be used in conjunction with HRDY to indicate that data is valid
in the external data latch.
HINT
O
Host Interrupt.
This signal allows the TMS34020 to interrupt a host by setting the INTOUT bit in the HSTCTLL I/O
register. This signal can also be used to interrupt the host if a BUSFLT or RETRY occurs due to a host-access cycle.
HOE
O
Host data-latch output-enable.
This signal enables data from host data latches to the TMS34020 local address
space on host-write cycles. HOE can be used in conjunction with HRDY to indicate data has been written to memory
from the external data latch.
HRDY
O
Host ready.
This signal is normally low and goes high to indicate that the TMS34020 is ready to complete a
host-initiated read or write cycle. If the TMS34020 is ready to accept the access request, HRDY is driven high and
the host proceeds with the access. A host can use HRDY logically combined with HDST and HOE to determine when
the local bus-access cycles have completed.
HREAD
I
Host read strobe.
This signal is driven low during a read request from a host processor. This notifies the TMS34020
that the host is requesting access to the I/O registers or to local memory. HREAD should not be asserted at the same
time that HWRITE is asserted.
HWRITE
I
Host write strobe.
This signal is driven low to indicate a write request by a host processor. This notifies the
TMS34020 that a write request is pending. The rising edge of HWRITE is used to indicate that the host has latched
data to be written in the external data transceivers. HWRITE should not be asserted at the same time HREAD is
asserted.
SYSTEM CONTROL
CLKIN
I
Clock input.
This system input clock generates the LCLK1 and LCLK2 outputs, to which all processor functions in
the TMS34020 are synchronous. A separate asynchronous input clock (VCLK) controls the video timing and video
registers.
LCLK1, LCLK2
O
Local output clocks.
These two clocks are 90 degrees out of phase with each other. They provide convenient
synchronous control of external circuitry to the internal timing. All signals output from the TMS34020 (except the CRT
timing signals) are synchronous to these clocks.
LINT1, LINT2
I
Local interrupt requests.
Interrupts from external devices are transmitted to the TMS34020 on LINT1 and LINT2.
Each local interrupt signal activates the request for one of two interrupt-request levels. An external device generates
an interrupt request by driving the appropriate interrupt-request pin to its active-low state. The signal should remain
low until the TMS34020 recognizes it. These signals can be applied asynchronously to the TMS34020; they are
synchronized internally before use.
RESET
I
System reset.
During normal operation, RESET is driven low to reset the TMS34020. When RESET is asserted
low, the TMS34020’s internal registers are set to an initial known state and all output and bidirectional pins are driven
either to inactive levels or to the high-impedance state. The TMS34020’s behavior following reset depends on the
level of the HCS input just before the low-to-high transition of RESET. If HCS is low, the TMS34020 begins executing
the instructions pointed to by the reset vector. If HCS is high, the TMS34020 is halted until a host processor writes
a 0 to the HLT bit in the HSTCTLL register.
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