參數(shù)資料
型號(hào)： TMS34020
廠(chǎng)商： Texas Instruments, Inc.
英文描述： GRAPHICS PROCESSORS
中文描述： 圖形處理器
文件頁(yè)數(shù)： 13/82頁(yè)
文件大?。?/td> 1359K
代理商： TMS34020
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
13
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
BIT 232 –1
(Last Bit in Memory)
68 Words
226 –66560 Words
(67 042 304 Words)
(3
×
226) –64K
(201 261 056 Words)
444 Words
65024 Words
512 Words
448 Words
64 Words
64K Words
Interrupt Vectors and
Extended Trap Vectors
Reserved for Interrupt Vectors
and Extended Trap Vectors
General Use and
Extended Trap Vectors
General Use and Extended
Trap Vectors
Bit 0
(First Bit in Memory)
General Use
Reserved for System I/O
Reserved for I/O Registers
I/O Registers
General Use
ADDRESS
FFFFFFF0h
FFFFFBC0h
FFFFFBB0h
FFFFE000h
FFFFDFF0h
FFF0000h
FFEFFFF0h
C0004000h
C0003FF0h
C0002000h
C0001FF0h
C0000400h
C00003F0h
C0000000h
BFFFFFF0h
00100000h
000FFFF0h
00000000h
16
Figure 1. Memory Map
reset
Reset puts the TMS34020 into a known initial state. This state is entered when the input signal at the RESET
pin is asserted low. While RESET remains asserted, all outputs are in a known state, no DRAM refresh cycles
take place, and no screen refresh cycles are performed.
The state of the HCS input on the CLKIN cycle before the low-to-high transition of the RESET signal determines
whether the TMS34020 will be halted or begin executing instructions. The TMS34020 may be in one of two
modes, host-present or self-bootstrap mode.
1.
Host-Present Mode. If HCS is high at the end of reset, TMS34020 instruction execution halts and remains
halted until the host clears the HLT (halt) bit in HSTCTLH (host control register). Following reset, the RAS
cycles required to initialize the dynamic RAMs are performed automatically by the GSP memory control
logic. The host may request a memory access after the eight RAS initialization cycles have completed. The
TMS34020 automatically performs DRAM refresh cycles at regular intervals; although the TMS34020
remains halted until the host clears the HLT bit. Only then does TMS34020 fetch the level-0 vector address
from location FFFFFFE0h and begin executing the reset service routine.
2.
Self-Bootstrap Mode. If HCS is low at the end of reset, the TMS34020 first performs eight refresh cycles
to initialize the DRAMs. Immediately following the eight refresh cycles, the GSP fetches the level-0 vector
address from location FFFFFFE0h, and begins executing the reset service routine.
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