
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
57
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
CLKIN and RESET timing requirements
NO.
PARAMETER
’34020-32
’34020A-32
’34020A-40
UNIT
MIN
MAX
MIN
MAX
1
tc(CKI)
tw(CKIH)
tw(CKIL)
tt(CKI)
th(CKI-RSL)
tsu(RSH-CKI)
Period of CLKIN (tQ)
Pulse duration, CLKIN high
31.25
50
25
50
ns
2
10
8
ns
3
Pulse duration, CLKIN low
10
2
10
4
8
ns
4
Transition time, CLKIN
5
2
10
4
5
ns
5
Hold time, RESET low after CLKIN high
Setup time, RESET high to CLKIN
↑
ns
6
ns
7
t(RSL)
tw(RSL)
Pulse
duration,
RESET low
Initial reset during power up
160tQ– 40§
16tQ– 40§
160tQ– 40§
16tQ– 40§
ns
Reset during active operation
8
tsu(CSL-RSH)
Setup time of HCS low to RESET high to configure
self-bootstrap mode
8tQ+55
8tQ+55
ns
9
td(CS-RSH)
Delay from HCS
↑
to RESET high to configure self-
bootstrap mode
4tQ– 50
4tQ– 50
ns
10
tw(CSL)
Pulse duration, HCS low to configure GSP in self-
bootstrap mode
4tQ+55
4tQ+55
ns
These values are based on computer simulation and are not tested.
These timings are required only to synchronize the TMS34020 to a particular quarter cycle.
§The initial reset pulse on power up must remain valid until all internal states have been initialized. Resets applied after the TMS34020 has been
initialized need to be present only long enough to be recognized by the internal logic; the internal logic will maintain an internal reset until all internal
states have been initialized (34 LCLK1 cycles).
Parameter 9 is the maximum amount by which the RESET low-to-high transition can be delayed after the start of the HCS low-to-high transition
and still assure that the TMS34020 is configured to run in the self-bootstrap mode (HLT bit = 0) following the end of reset.
2
1
3
4
4
5
6
7
8
9
10
HCS
CLKIN
RESET
Figure 33. CLKIN and RESET Timing Requirements