參數(shù)資料
型號： TMS34020
廠商： Texas Instruments, Inc.
英文描述： GRAPHICS PROCESSORS
中文描述： 圖形處理器
文件頁數(shù)： 11/82頁
文件大?。?/td> 1359K
代理商： TMS34020
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
11
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
I/O registers
The TMS34020 contains an on-chip block of sixty-four 16-bit locations (mapped into the TMS34020’s memory
address space) that are used for I/O control registers. Eight of these are used by the host interface logic and
are not available to the user. Forty-seven I/O registers control parameters necessary to configure the operation
and report status of the following interfaces:
Host interface.
Local memory.
Video timing.
Screen refresh.
External interrupts.
Internal interrupts.
host interface registers
The host interface registers (HSTDATA, HSTADRL, HSTADRH, HSTCTLL, and HSTCTLH) are provided to
facilitate communications between the TMS34020 and a host processor and maintain compatibility with the
TMS34010. The registers are mapped into five of the I/O locations accessible to the TMS34020.
Two of these registers (HSTCTLL and HSTCTLH) are used to provide control by the host. This control consists
of passing of interrupt requests, flushing the instruction cache, halting the TMS34020, transmitting a
nonmaskable interrupt request to the TMS34020, enabling emulation interrupts, and setting host-access modes
and configurations.
The other three registers are simple read/write registers to allow the TMS34020 software to leave addresses
for the host at a known location and allow compatibility with some TMS34010 software.
memory interface control registers
Some of the I/O registers are used to control various local memory interface functions, including:
Frequency of DRAM refresh cycles.
Masking (read/write protection) of individual color planes.
DRAM row/column addressing configuration.
Accessing mode (big endian/little endian).
Bus fault and retry recovery.
video timing and screen refresh
Twenty-eight I/O registers are dedicated to video timing and screen refresh functions. The TMS34020 can be
configured to drive composite sync or separate sync displays.
In composite mode, the TMS34020 can be set to extract VSYNC and HSYNC from an external CSYNC, or it
can be used to generate CSYNC from separate VSYNC and HSYNC inputs. Internally, the TMS34020 can be
set to preset the horizontal and vertical counts on receipt of an external sync signal. This allows compensation
for any combination of internal and external delays that occur in the video synchronization process. The
HCOUNT register is loaded from SETHCNT by an external HSYNC, VCOUNT is loaded from SETVCNT on an
external VSYNC, and an external CSYNC loads both HCOUNT and VCOUNT from SETHCNT and SETVCNT,
respectively.
The TMS34020 directly supports multiport video RAMs (VRAMs) by generating the serial data register transfer
cycles necessary to refresh the display. The memory locations from which the display information is taken, as
well as the number of horizontal scan lines displayed between serial data register transfer cycles, are
programmable.
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