參數(shù)資料
型號: TMS34020
廠商: Texas Instruments, Inc.
英文描述: GRAPHICS PROCESSORS
中文描述: 圖形處理器
文件頁數(shù): 52/82頁
文件大小: 1359K
代理商: TMS34020
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
52
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
GI
ALTCH
RAS
WE
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
R1
LAD
Command
CAMD
CAS
TR/QE
SF
DDIN
DDOUT
R0
PGMD
SIZE16
LRDY
BUSFLT
RCA
LCLK1
LCLK2
(TMS34020)
Command Cycle
NOTES: A. All coprocessor cycles are implemented as 32-bit operations; therefore, SIZE16 should be high during these cycles.
B. LAD (TMS34020):
Output to the LAD bus by the TMS34020
command:
Coprocessor ID, instruction and status code present on LAD
C. Although the coprocessor internal command never requires the use of page mode cycles, PGMD should be held at a valid level
during the start of Q2 after ALTCH has gone low.
Figure 29. Coprocessor Internal Operation Command Cycle
This timing example is like a memory write cycle, except that RAS and SF are high.
A coprocessor internal command assumes no transfer of operands or results but causes the coprocessor to
execute some internal function. The coprocessor can place status information on the LAD bus during the cycle
for the TMS34020.
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