
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
8
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Terminal Functions (Continued)
VIDEO INTERFACE
NAME
I/O
DESCRIPTION
HSYNC
I/O
Horizontal sync. HSYNC
is the horizontal sync signal that controls external video circuitry. You can program this
signal to be either an input or an output by modifying a control bit in the DPYCTL register.
As an
output,
HSYNC is the active-low horizontal-sync signal generated by the TMS34020’s on-chip video
timers.
As an
input
, HSYNC synchronizes the TMS34020 video-control registers to externally generated horizontal-sync
pulses. The actual synchronization can be programmed to begin at any VCLK cycle; this allows for any external
pipelining of signals.
Immediately following reset, HSYNC is configured as an input.
SCLK
I
Serial data clock.
This signal is the same as the signal that drives VRAM serial data registers. This allows the
TMS34020 to track the VRAM serial data register count, providing serial-register-transfer and midline-reload cycles.
(SCLK can be asynchronous to VCLK; however, it typically has a frequency that is a multiple of the VCLK frequency).
VCLK
I
Video clock.
This clock is derived from a multiple of the video system’s dotclock and is used internally to drive the
video timing logic.
VSYNC
I/O
Vertical sync. VSYNC
is the vertical sync signal that controls external video circuitry. You can program this signal
to be either an input or an output by modifying a control bit in the DPYCTL register.
As an
output,
VSYNC is the active-low vertical-sync signal generated by the TMS34020’s on-chip video timers.
As an
input
, VSYNC synchronizes the TMS34020 video-control registers to externally generated vertical-sync
pulses. The actual synchronization can be programmed to begin at any horizontal line; this allows for any external
pipelining of signals.
Immediately following reset, VSYNC is configured as an input.