參數(shù)資料
型號: TMS34020
廠商: Texas Instruments, Inc.
英文描述: GRAPHICS PROCESSORS
中文描述: 圖形處理器
文件頁數(shù): 37/82頁
文件大小: 1359K
代理商: TMS34020
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
37
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Q4
Q1
Q2
Q3
Q4*
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Row
Address
Tap Point
Address
Subcycle
Wait
State
Cycle
Completion
GI
LAD
CAMD
RCA
ALTCH
RAS
CAS
WE
TR/QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
*See clock stretch, page 21.
Figure 14. Memory-to-Serial-Data-Register Cycle (VRAM Read Transfer)
This VRAM cycle is issued in any of three ways:
1.
2.
3.
Pixel operation instruction with the CST bit in DPYCTL set.
Horizontal blank reload cycle requested by the video-control logic with the VCE bit in DPYCTL cleared.
Video timeout due to SCOUNT match with the value in MLRNXT and the VCE and SSV bits in DPYCTL
cleared.
This cycle is indicated by TR/QE and SF low and CAS and WE high at the time RAS goes low. The timing of
the low-to-high transition of TR/QE is dependent upon the timing of SCLK when doing a midline reload cycle.
During the address portion of the cycle, the status on LAD0–LAD3 indicates either a video-initiated VRAM
memory-to-register transfer (status code = 0100) or a CPU-initiated VRAM memory-to-register transfer
(status code = 0101).
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