參數(shù)資料
型號(hào): TMS34020
廠(chǎng)商: Texas Instruments, Inc.
英文描述: GRAPHICS PROCESSORS
中文描述: 圖形處理器
文件頁(yè)數(shù): 26/82頁(yè)
文件大?。?/td> 1359K
代理商: TMS34020
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
26
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
LCLCK1
LCLCK2
GI
LAD (TMS34020)
LAD (Memory)
CAMD
RCA
ALTCH
RAS
CAS
WE
TR/QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
Q4
Q1
Q2
Q3
Q4*
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Address
Column
Address Subcycle
Wait State
Read Transfer
Data
Row
*See clock stretch, page 21.
NOTES: A. LAD (TMS34020): Output to the LAD bus by the TMS34020. LAD (memory): Output to the LAD bus by the memory.
B. Although they are not internally sampled, PGMD and SIZE16 must be held at a valid level at the start of each Q2 until the LRDY
is sampled high.
Figure 3. Local Memory Read Cycle Timing (Without Page Mode, With One Wait State)
LRDY low at the start of the first Q2 after RAS low indicates that the memory requires the addition of wait states.
LRDY high at the next Q2 indicates the cycle can continue without inserting more wait states. PGMD high at
the start of Q2 where LRDY is sampled high indicates that this memory does not support page-mode operation.
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