參數(shù)資料
型號(hào)： TMS34020
廠商： Texas Instruments, Inc.
英文描述： GRAPHICS PROCESSORS
中文描述： 圖形處理器
文件頁(yè)數(shù)： 20/82頁(yè)
文件大?。?/td> 1359K
代理商： TMS34020
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
20
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
The TMS34020 always accesses the required location as latched at the falling edge of HCS; however, in order
to increase the data rate, a look-ahead mechanism is implemented. The HINC (host increment enable) and
HPFW (host prefetch after write enable) bits in the host control register (HSTCTLH) must be appropriately set
to make optimum use of this feature. These bits provide four modes of operation as indicated in the following
table:
HINC
HPFW
HOST ACCESS MODE
DESCRIPTION
0
0
RANDOM/SAME
No increment, no prefech
0
1
RANDOM/SAME
No increment, no prefetch
1
0
BLOCK
Increment after read or write, prefetch after read
1
1
READ/MODIFY/WRITE
Increment after write, prefetch after write
When the TMS34020 is programmed for block-mode or read/modify/write accesses, the host can still do random
accesses because the TMS34020 always uses the address provided at the falling edge of HCS; however, there
is a prefetch to the next sequential address. The prefetch occurs after reads in block mode and after writes in
read/modify/write mode. The TMS34020 compares the address latched by HCS on host reads to see if it is the
same as that of the last prefetched data. If the addresses match, data is not reaccessed, but HRDY is set high
to indicate that the data is presently available.
dynamic bus sizing on host accesses
If the host makes a read access to a 16-bit-wide memory, the TMS34020 automatically does the second cycle
required to read the rest of the 32-bit word (even if the host did not require a 32-bit cycle). The external logic
must comprehend the sense of SIZE16 or the CAS strobes during the accesses in order to route the data into
the proper external host data transceivers. The TMS34020 uses the host byte selects (HBS0–HBS3) to enable
the CAS strobes when doing a host write.
coprocessor interface
Support for coprocessors is provided through special instructions and bus cycles that allow communication with
the coprocessor. A coprocessor may be register-based, depending on the TMS34020 to do all address
calculations, or it may operate as its own bus controller, using the multiprocessor arbitration scheme. Five basic
cycles are provided for direct communication and control of coprocessors.
1.
2.
3.
4.
5.
TMS34020 to coprocessor.
Coprocessor to TMS34020.
Move memory to coprocessor.
Move coprocessor to memory.
Coprocessor internal command.
The first four of these cycles provide for command of the coprocessor in addition to the movement of parameters
to and from the coprocessor. In this manner, parameters can be sent to the coprocessor and operated upon
without an explicit coprocessor command cycle.
相關(guān)PDF資料
PDF描述
TMS3450NL LED DUPLEX DIGITAL RADIO CLOCK
TMS3471CFS 780- 】 488-pixel ccd image sensor
TMS3471 2/3-INCH NTSC TIMER
TMS3473 PARALLEL DRIVER
TMS370C036A 8-BIT MICROCONTROLLER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TMS3450NL 制造商:Rochester Electronics LLC 功能描述:- Bulk
TMS3459BNL 制造商:Panasonic Industrial Company 功能描述:IC
TMS3471C 制造商:Rochester Electronics LLC 功能描述:- Bulk
TMS3472ADW 制造商:Rochester Electronics LLC 功能描述:- Bulk
TMS3637D 制造商:Rochester Electronics LLC 功能描述:- Bulk
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*