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參數(shù)資料
| 型號： | TMS34020 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | GRAPHICS PROCESSORS |
| 中文描述： | 圖形處理器 |
| 文件頁數(shù)： | 24/82頁 |
| 文件大?。?/td> | 1359K |
| 代理商： | TMS34020 |
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TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
24
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
a clock-stretch timing example, TMS34020A-40 and 100-ns VRAMs
This example analyzes a memory interface timing parameter. It shows that the clock stretch mechanism can
be used to allow the TMS34020A-40 to avoid a timing violation when interfaced to 100-ns VRAMs.
Consider a system with:
1.
TMS34020A-40,
which has a 40-MHz clock input frequency and hence a 100-ns cycle time, so
t
Q
= 25 ns. Timing parameters are taken from the TMS34020 data sheet.
256K
×
4 bit VRAM. Timing parameters are taken from the appropriate section in
the Texas Instruments MOS Memory Data Book 1989.
2.
TMS44C251-10
row address hold data after RAS low, t
h(ADV-REL)
Without clock stretch
TMS44C251
TMS34020A
t
h(RA)
Parameter 88
Row address hold time after RAS low.
Hold time, row address valid after RAS low.
Min = 15 ns
Min = t
Q
– 5 ns = 20 ns.
If RAS is passed through a PAL
with a delay of 7 ns then t
h(RA)
seen by the VRAM is 20 ns – 7 ns = 13 ns.
This violates the 15 ns minimum.
With clock stretch
TMS34020A
Parameter 88
Hold time, row address valid after RAS low.
Min = 2t
Q
– 5 ns = 45 ns.
With the same 7-ns PAL delay, the VRAM sees t
h(RA)
as 45 ns – 7ns = 38 ns, which does not violate the VRAM
minimum of 15 ns.
cycle timing examples
The following figures show examples of many of the basic cycles that the TMS34020 uses for memory access,
VRAM control, multiprocessor bus control, and coprocessor communication. These figures should not be used
to determine specific signal timings, but can be used to see signal relationships for the various cycles. Q4 phases
that couldbe stretched are marked with a * on the diagrams. The conditions required for the stretch are:
1.
2.
3.
The design uses a TMS34020A
The CONFIG register’s CSE bit is set to 1
The TMS34020A is doing either:
a)
Any address cycle, or
b)
A read data cycle in a read-modify-write sequence.
The following remarks apply to memory timing in general. A row address is output on RCA0–RCA12 at the start
of a cycle, along with the full address and status on LAD0–LAD31. These remain valid until after the fall of
ALTCH and RAS. The column address is then output on RCA0–RCA12, and LAD0–LAD31 are set to read or
write data for the memory access. During a write, the data and WE are set valid prior to the falling edge of CAS;
the data remains valid until after WE and CAS have returned high.
Large memory configurations may require external buffering of the address and data lines. The DDIN and
DDOUT signals coordinate these external buffers with the LAD bus.
PAL is a trademark of Advanced Micro Devices, Inc.
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