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參數(shù)資料
| 型號： | TMS34020 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | GRAPHICS PROCESSORS |
| 中文描述： | 圖形處理器 |
| 文件頁數(shù)： | 35/82頁 |
| 文件大?。?/td> | 1359K |
| 代理商： | TMS34020 |
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TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
35
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Q4
Q1
Q2
Q3
Q4*
Q1
Q2
Q3
Q4
Q1
Row
Address
Data Out 1
Q2
Q3
Q4
Q1
Data Out 2
1st Column
2nd Column
GI
LAD
CAMD
RCA
ALTCH
RAS
CAS
WE
TR/QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
*See clock stretch, page 21.
Figure 12. Block-Write Cycle With Mask
This special 1M VRAM control cycle is performed when a VBLT or VFILL instruction is executed and PMASKL
and PMASKH are set to nonzero. It is indicated by CAS, TR/QE, and SF high and WE low at the falling edge
of RAS, and by SF high at the falling edge of CAS. The data on LAD is used as an address mask, and the data
stored in the color latch is written to the VRAM, just as in the block-write cycle without mask, except that the data
in the write mask is used to enable the bits from the color latch that are written to memory. This cycle allows up
to 16 bits to be written into each VRAM (four adjacent nibbles, each set to the value in the color latch as enabled
by the write mask) for a total of 128 bits. During the address portion of the cycle, the status on LAD0–LAD3
indicates a block write is being performed (status code = 1110). SIZE16 can be used with this cycle, but external
multiplex logic is required to map the data correctly to appropriate memories.
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