參數(shù)資料
型號(hào)： TMS34020
廠商： Texas Instruments, Inc.
英文描述： GRAPHICS PROCESSORS
中文描述： 圖形處理器
文件頁數(shù)： 5/82頁
文件大?。?/td> 1359K
代理商： TMS34020
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
5
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Terminal Functions
LOCAL MEMORY INTERFACE
NAME
I/O
DESCRIPTION
ALTCH
O
Address latch.
The high-to-low transitions of ALTCH can be used to capture the address and status present of the LAD
signals. A transparent latch (such as a 74ALS373) maintains the current address and status as long as ALTCH remains
low.
BUSFLT
I
Bus fault.
External logic asserts BUSFLT high to the TMS34020 to indicate that an error or fault has occurred on the
current bus cycle. BUSFLT is also used with LRDY to generate externally requested bus cycle retries so that the entire
memory address is presented again on the LAD pins. In emulation mode, BUSFLT is used for write-protecting mapped
memory (by disabling CAS outputs for the current cycle).
DDIN
O
Data bus direction in enable.
This active-high output is used to drive the active-high output-enables on bidirectional
transceivers (such as the 74ALS623). The transceivers buffer data input and output on the LAD0–LAD31 pins when
the TMS34020 is interfaced to several memories.
DDOUT
O
Data bus direction output-enable.
This active-low signal drives the active-low output-enables on bidirectional
transceivers (such as the 74ALS623). The transceivers buffer data input and output on the LAD0–LAD31 pins.
LAD0–LAD31
I/O
32-bit multiplexed local address/data bus.
At the beginning of a memory cycle, the word address is output on
LAD4–LAD31 and the cycle status is output on LAD0–LAD3. After the address is presented, LAD0–LAD31 are used
for transferring data within the TMS34020 system. LAD0 is the LSB and LAD31 is the MSB.
LRDY
I
Local ready.
External circuitry drives this signal low to inhibit the TMS34020 from completing a local-memory cycle it
has initiated. While LRDY remains low, the TMS34020 will wait unless the TMS34020 loses bus priority or is given an
external RETRY request (through the BUSFLT signal). Wait states are generated in increments of one full LCLK1 cycle.
LRDY can be driven low to extend local-memory read and write cycles, VRAM serial-data-register transfer cycles, and
DRAM refresh cycles. During internal cycles, the TMS34020 ignores LRDY.
PGMD
I
Page mode.
The memory decode logic asserts this signal low if the currently addressed memory supports burst
(page-mode) accesses. Burst accesses occur as a series of CAS cycles for a single RAS cycle to memory. LRDY is
used with BUSFLT to describe the cycle termination status for a memory cycle. PGMD is also used in emulation mode
for mapping memory.
SIZE16
I
Bus size.
The memory decode logic can pull this signal low if the currently addressed memory or port supports only
16-bit transfers. SIZE16 can also be used to determine which 16 bits of the data bus are used for a data transfer.
In emulation mode, SIZE16 is used to select the size of mapped memory.
DRAM AND VRAM CONTROL
CAMD
I
Column-address mode.
This input dynamically shifts the column address on the RCA0–RCA12 bus to allow the
mixing of DRAM and VRAM address matrices using the same multiplexed address RCA0–RCA12 signals.
CAS0–CAS3
O
4 column-address strobes.
The CAS outputs drive the CAS inputs of DRAMs and VRAMs. These signals strobe the
column address on RCA0–RCA12 to the memory. The four CAS strobes provide byte-write access to the memory.
RAS
O
Row-address strobe.
The RAS output drives the RAS inputs of DRAMs and VRAMs. This signal strobes the row
address on RCA0–RCA12 to memory.
RCA0–RCA12
O
13 multiplexed row-address/column-address signals.
At the beginning of a memory-access cycle, the row address
for DRAMs is present on RCA0–RCA12. The row address contains the most significant address bits for the memory.
As the cycle progresses, the memory column address is placed on RCA0–RCA12. The addresses that are actually
output during row and column times depend on the memory configuration (set by RCM0 and RCM1 in the CONFIG
register) and the state of CAMD during the access. RCA0 is the LSB and RCA12 is the MSB.
SF
O
Special-function pin.
This is the special-function signal to 1M VRAMs that allows the use of block write, load write
mask, load color mask, and write using write mask. This signal is also used to differentiate instructions and addresses
for the coprocessor as part of the coprocessor interface.
TR/QE
O
Transfer/output-enable.
This signal drives the TR/QE input of VRAMs. During a local-memory read cycle, TR/QE
functions as an active-low output-enable to gate from memory to LAD0–LAD31. During special VRAM function cycles,
TR/QE controls the type of cycle that is performed.
WE
O
Write-enable.
The active low WE output drives the WE inputs of DRAMs and VRAMs. WE can also be used as the
active-low write-enable to static memories and other devices connected to the TMS34020 local interface. During a
local-memory read cycle, WE remains inactive high while CAS is strobed active low. During a local-memory write cycle,
WE is strobed active low before CAS is. During VRAM serial-data-register transfer cycles, the state of WE at the falling
edge of RAS controls the direction of the transfer.
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