參數(shù)資料
型號: TMS34020
廠商: Texas Instruments, Inc.
英文描述: GRAPHICS PROCESSORS
中文描述: 圖形處理器
文件頁數(shù): 42/82頁
文件大小: 1359K
代理商: TMS34020
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
42
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
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GSP1 Read
GSP2 Write
GSP1 Read With Wait
Bus Idle
GSP1
GI
R0
R1
RAS
CAS
WE
TR/QE
DDIN
DDOUT
ALTCH
LRDY
ALTCH
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R0
R1
RAS
CAS
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TR/QE
DDIN
DDOUT
GSP2
Figure 19. Multiprocessor Interface Timing (Passing Control)
Two TMS34020s use the multiprocessor interface to pass control of local memory from one to the other. GSP1
completes a read cycle to the local memory and, although desiring another read, loses the bus to GSP2, which
does a single write cycle (perhaps a host-write access). GSP1 then regains control and completes the read cycle
(shown with a single wait state). Since no further memory-access requests are present, GSP1 maintains control
of the bus and holds all of the local-memory control signals at their inactive levels. LRDY is a common input to
both GSP1 and GSP2.
The host cycle timing diagrams shown in this data sheet are only a sample. If you want more information, see
the TMS34020 User’s Guide
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