
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
71
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
CAS-before-RAS refresh: RAS and CAS0–CAS3
NO.
PARAMETER
’34020-32
’34020A-32
’34020A-40
UNIT
MIN
MAX
tQ+12
tQ+12
tQ+12
tQ+12
MIN
MAX
tQ+10
tQ+10
tQ+10
tQ+10
76
td(CK1
↓
-REL)
td(CK1
↓
-REH)
td(CK1
↑
-CEL)
td(CK1
↓
-CEH)
td(REL-CE
↑
)
td(REL-CE
↑
)
td(CEL-RE
↓
)
td(REH-CE
↓
)
Delay time, RAS low after LCLK1
↓
Delay time, RAS high after LCLK1
↓
Delay time, CAS low after LCLK1
↑
Delay time, CAS high after LCLK1
↓
Delay time, RAS low to CAS
↑
Delay time, RAS low to CAS
↑
Delay time, CAS low to RAS
↓
Delay time, RAS high to CAS
↓
ns
77
ns
78
ns
79
ns
102a
4tQ–12+ s
4tQ–12
2tQ–15
2tQ–15+ s
4tQ – 4+ s
4tQ – 4
2tQ – 13.5
2tQ –13.5+ s
ns
102b
ns
103
ns
104
ns
DDOUT
RCA
LAD
ALTCH
CAS
RAS
LCLK2
LCLK1
Refresh Pseudo-Address
Refresh Pseudo-Address
Q1
Q2
Q3
Q4*
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
79
102b
103
77
76
78
104
*See clock stretch, page 21.
NOTE A: ALTCH, LAD, RCA, and DDOUT are shown for reference only.
Figure 43. CAS-Before-RAS Refresh: RAS and CAS0–CAS3
The refresh pseudo-address present on LAD0–LAD31 is the output from the 16-bit refresh address register (I/O
register located at C000 01F0h) on LAD16–LAD31. LAD0–LAD3 have the refresh status code
(status code = 0011), and LAD4–LAD15 are held low.