- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385001 > TMS34020 (Texas Instruments, Inc.) GRAPHICS PROCESSORS PDF資料下載
參數(shù)資料
| 型號： | TMS34020 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | GRAPHICS PROCESSORS |
| 中文描述： | 圖形處理器 |
| 文件頁數(shù)： | 51/82頁 |
| 文件大小： | 1359K |
| 代理商： | TMS34020 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁當(dāng)前第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
51
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
LCLK1
LCLK2
CAMD
RCA
LAD
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
LAD
Command
Q2
Q3
Q4*
Q1
SF
DDIN
Data 1
LRDY
BUSFLT
Address
Data 2
2nd Column
1st Column
Row
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
(TMS34020)
Coprocessor)
Status
GI
ALTCH
RAS
CAS
WE
TR/QE
DDOUT
PGMD
SIZE16
R0
R1
Command Cycle
Address
Data Tansfer
Data Transfer
Spacer
*See clock stretch, page 21.
NOTES: A. All coprocessor cycles are implemented as 32-bit operations; therefore, SIZE16 should be high during these cycles.
B. LAD (TMS34020):
Output to the LAD bus by the TMS34020
LAD (coprocessor):
Output to the LAD bus by the coprocessor
Command:
Coprocessor ID, instruction and status code present on LAD
Address:
Memory address for the data transfer, with coprocessor status code
Data n:
Data from the coprocessor (number of values transferred depends on a count in the instruction)
Status:
Optional coprocessor status register output to LAD bus
Figure 28. Transfer Coprocessor Register(s) to Memory (ALTCH High During Data Transfer)
Data transfer from a coprocessor to memory requires an initialization cycle to inform the coprocessor what is
to be transferred and then a memory cycle to perform the actual transfer. The coprocessor can place status
information on the LAD bus during the initialization cycle for the TMS34020. The memory cycle includes a dead
cycle to enable the TMS34020 to take the LAD bus drivers to the high-impedance state before the coprocessor
activates its LAD bus drivers to the memory. Two types of memory-to-coprocessor instructions are supported.
Both provide a count (from 1 to 32) of data to be moved in the instruction. Both also specify a register to be used
as an index into memory. One uses this index register with a post-increment and the other uses it with a
pre-decrement after each transfer cycle.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TMS3450NL | LED DUPLEX DIGITAL RADIO CLOCK |
| TMS3471CFS | 780- 】 488-pixel ccd image sensor |
| TMS3471 | 2/3-INCH NTSC TIMER |
| TMS3473 | PARALLEL DRIVER |
| TMS370C036A | 8-BIT MICROCONTROLLER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMS3450NL | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TMS3459BNL | 制造商:Panasonic Industrial Company 功能描述:IC |
| TMS3471C | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TMS3472ADW | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TMS3637D | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。