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參數(shù)資料
| 型號： | TMS34020 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | GRAPHICS PROCESSORS |
| 中文描述： | 圖形處理器 |
| 文件頁數(shù)： | 46/82頁 |
| 文件大?。?/td> | 1359K |
| 代理商： | TMS34020 |
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TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
46
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Q4
Q1
Q2
Q3
Q4*
Q1
Q2
Q3
Q4
Q1
Row
Column
1 st write valid
Local-Memory Host Write Cycle
Q2
Q3
Q4*
Q1
Q2
Q3
Q4
Q1
Row
Column
1st Address
2nd Address
Local-Memory Host Prefetch
valid
previous read
HA/HBS
HCS
HREAD
HWRITE
HRDY
HOE
HDST
LAD
GI
CAMD
RCA
SF
ALTCH
RAS
CAS
WE
TR/QE
DDIN
DDOUT
LRDY
SIZE16
PGMD
BUSERR
R0
R1
DATA
(out)
D(in)
*See clock stretch, page 21.
NOTE A: HRDY goes high at the start of Q2; however, the memory cycle writing data to memory is not completed until the start of Q4 when ALTCH,
CAS, and HOE return high. The host must not strobe new data into the external latch until just after the start of Q4.
Figure 23. Host Write Cycle Back-to-Back With Prefetch of Next Word and Implicit Addressing; HREAD
and HWRITE Used as Strobes
The TMS34020 provides HRDY as soon as it recognizes the host write cycle (if no other host write cycle is in
progress), allowing the host to latch the data in the external data latches. The host then attempts a second write
but does not get an immediate HRDY because the TMS34020 is still writing the first data to memory. As soon
as the memory write completes, HRDY goes high so that the host can latch the new data. The TMS34020 then
writes the second data while the host continues other processing. The host access request is synchronized to
the TMS34020 at the beginning of Q4 so that the local memory cycle can begin in Q1. If the external host access
request occurs after the setup time requirement before Q4, the request is not considered until the next Q4 cycle.
During a host write cycle DDIN is active so that if the write is to the TMS34020 I/O registers, the data can be
required within the GSP.
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