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參數(shù)資料
| 型號： | TMS34020 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | GRAPHICS PROCESSORS |
| 中文描述： | 圖形處理器 |
| 文件頁數(shù)： | 2/82頁 |
| 文件大小： | 1359K |
| 代理商： | TMS34020 |
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TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
2
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
description
The TMS34020 and the TMS34020A graphics processors are the second generation of an advanced
high-performance CMOS 32-bit microprocessor optimized for graphics display systems. With a built-in
instruction cache, the ability to simultaneously access memory and registers, and an instruction set designed
to expedite raster graphics operations, the TMS34020 and TMS34020A provide user-programmable control of
the CRT interface as well as the memory interface (both standard DRAM and multiport video RAM). The
4-gigabit (512-megabyte) physical address space is addressable on bit boundaries using variable-width data
fields (1 to 32 bits). Additional graphics addressing modes support 1-, 2-, 4-, 8-, 16- and 32-bit wide pixels.
The information contained in this data sheet is applicable to both the TMS34020 and the TMS34020A, except
that pertaining to clock stretch, which begins on page 21. Use of the term TMS34020 shall refer to both devices
except where noted.
architecture
The TMS34020 is a CMOS 32-bit processor with hardware support for graphics operations such as PixBlts
(raster ops) and curve-drawing algorithms. Also included is a complete set of general-purpose instructions with
addressing modes tuned to support high-level languages. In addition to its ability to address a large external
memory range, the TMS34020 contains 30 general-purpose 32-bit registers, a hardware stack pointer, and a
512-byte instruction cache. On-chip functions include 64 programmable I/O registers that control CRT timing,
input/output control, and parameters required by some instructions. The TMS34020 directly interfaces to
dynamic RAMs and video RAMs and generates raster control signals. The TMS34020 can be configured to
operate as a standalone processor, or it can be used as a graphics engine with a host system. The host interface
provides a generalized communication port for any standard host processor. The TMS34020 also
accommodates a multiprocessing or direct memory access (DMA) environment through the request/grant
interface protocols. Virtual memory systems are supported through bus-fault detection and instruction
continuation.
The TMS34020 provides single-cycle execution of general-purpose instructions and most common integer
arithmetic and Boolean operations from its instruction cache. Additionally, the TMS34020 incorporates a
hardware barrel shifter that provides a single-state bidirectional shift-and-rotate function for 1 to 32 bits.
The local-memory controller is designed to optimize memory-access operations. It also supports pipeline
memory-write operations of variable-sized fields and allows memory access and instruction execution in
parallel.
The TMS34020 graphics processing hardware supports pixel and pixel-array processing capabilities for both
monochrome and color systems at a variety of pixel sizes. The hardware incorporates two-operand and
three-operand raster operations with Boolean and arithmetic operations, XY addressing, window clipping,
window-checking operations, 1 to n bits-per-pixel transforms, transparency, and plane masking. The
architecture further supports operations on single pixels (PIXT instructions) or on two-dimensional arrays of
arbitrary size (PixBlts).
The TMS34020’s flexible graphics processing capabilities allow software-based graphics algorithms without
sacrificing performance. These algorithms include clipping to arbitrary window size, custom incremental curve
drawing, two-operand raster operations, and masked two-operand raster operations.
The TMS34020 provides for extensions to the basic architecture through the coprocessor interface. Special
instructions and cycle timings are included to enhance data flow to coprocessors, such as the TMS34082
floating-point unit, without requiring the coprocessor to decode the instruction stream, generate system
addresses, or move data for the coprocessor through the TMS34020.
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