參數(shù)資料
型號： TMS34020
廠商： Texas Instruments, Inc.
英文描述： GRAPHICS PROCESSORS
中文描述： 圖形處理器
文件頁數(shù)： 40/82頁
文件大?。?/td> 1359K
代理商： TMS34020
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
40
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Q4
Q1
Q2
Q3
Q4*
Q1
Q2
Q3
Q4
Q1
Row
Address
Tap Point
GI
LAD
CAMD
RCA
ALTCH
RAS
CAS
WE
TR/QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
*See clock stretch, page 21.
Figure 17. Serial-Data-Register-to-Memory Cycle (VRAM Alternate-Write Transfer)
This VRAM cycle is performed when a pixel-write instruction is executed with the CST bit in DPYCTL set. This
cycle is indicated by TR/QE and WE low, and SF and CAS high at the time RAS goes low. This cycle does not
require the use of the SOE pin of the VRAM and does not affect the status of the serial I/O pins. During the
address portion of the cycle, the status on LAD0–LAD3 indicates that a CPU-initiated VRAM
register-to-memory transfer (status code = 0101) is being performed. Although PGMD and SIZE16 are ignored
on this cycle, they should be held at valid levels as shown.
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