參數(shù)資料
型號： TMS34020
廠商： Texas Instruments, Inc.
英文描述： GRAPHICS PROCESSORS
中文描述： 圖形處理器
文件頁數(shù)： 41/82頁
文件大?。?/td> 1359K
代理商： TMS34020
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
41
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Row
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
Host-Default
Cycle
Beginning
of Cycle
LCLK1
LCLK2
LAD
GI
R0
R1
CAMD
RCA
SF
ALTCH
RAS
CAS
WE
TR/QE
DDIN
DDOUT
LRDY
SIZE16
PGMD
BUSFLT
HOE
HDST
Figure 18. Multiprocessor Interface Timing (High-Impedance Signals)
Transition points are shown for R0 and R1 to indicate where they occur relative to the other signals.
This example indicates that the TMS34020 has control of the bus, yields control, and then regains control. The
TMS34020 regains bus mastership as soon as its GI pin is driven active (low). R0 and R1 could be outputting
any of the codes with the exception of the access-termination code. The bus arbitration logic must control the
timing of GI to all of the processors requiring the bus.
It is recommended that TMS34020A clock stretch not be used in multiprocessor systems.
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